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Optimal wiring between rectangles

Published: 11 May 1981 Publication History

Abstract

We consider the problem of wiring together two parallel rows of points under a variety of conditions. The options include whether we allow the rows to slide relative to one another, whether we use only rectilinear wires or arbitrary wires, and whether we can use wires in one layer or several layers. In almost all of these combinations of conditions, we can provide a polynomial-time algorithm to minimize the distance between the parallel rows of points. We also compare two fundamentally different wiring approaches, where one and two layers are used. We show that although the theoretical model implies that there can be great gains for the two-layer strategy, even in cases where no crossovers are required, when we consider typical design rules for laying out VLSI circuits there is no substantial advantage to the two-layer approach over the one-layer approach.

References

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Dolev, D. and A. Siegel, report in preparation.
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Fischer, M. J. and M. S. Paterson, "Optimal tree layout," Proc. Twelfth Annual ACM Symposium on the Theory of Computing, pp. 177-189, 1980.
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Johannsen, D., "Bristle blocks: a silicon compiler," Caltech Conf. on VLSI, pp. 303-310, Jan., 1979. See also Sixteenth Design Automation Proceedings, pp. 310-313, June, 1979.
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LaPaugh, A. S, "A polynomial time algorithm for optimal routing around a rectangle," Proc. Twenty-first Annual IEEE Symposium on Foundations of Computer Science, pp. 282-293, 1980.
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Mead, C. and L. Conway, Introduction to VLSI Systems, Addison Wesley, Reading, Mass.
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Shamos, M. I., "Geometry and statistics: problems at the interface," in Algorithms and Complexity, J. F. Traub, ed., Academic Press, 1976.
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Storer, J. A., "The node cost measure for embedding graphs on the planar grid," Proc. Twelfth Annual ACM Symposium on the Theory of Computing, pp. 201-210, 1980.
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Tompa, M., "An optimal solution to a wire-routing problem," Proc. Twelfth Annual ACM Symposium on the Theory of Computing, pp. 161-176, 1980.
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Valiant, L., "Universality considerations in VLSI circuits," CSR-54-80, Dept. of CS, Univ. of Edinburgh, 1980.

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  • (2020)Rectilinear routing algorithm for crosstalk minimisation in 2D and 3D ICIET Computers & Digital Techniques10.1049/iet-cdt.2020.001014:6(263-271)Online publication date: 18-Sep-2020
  • (2016)On the Three-Dimensional Channel RoutingIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E99.A.1813E99.A:10(1813-1821)Online publication date: 2016
  • (2010)VLSI layout algorithmsAlgorithms and theory of computation handbook10.5555/1882723.1882731(8-8)Online publication date: 1-Jan-2010
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cover image ACM Conferences
STOC '81: Proceedings of the thirteenth annual ACM symposium on Theory of computing
May 1981
390 pages
ISBN:9781450373920
DOI:10.1145/800076
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 11 May 1981

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Cited By

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  • (2020)Rectilinear routing algorithm for crosstalk minimisation in 2D and 3D ICIET Computers & Digital Techniques10.1049/iet-cdt.2020.001014:6(263-271)Online publication date: 18-Sep-2020
  • (2016)On the Three-Dimensional Channel RoutingIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E99.A.1813E99.A:10(1813-1821)Online publication date: 2016
  • (2010)VLSI layout algorithmsAlgorithms and theory of computation handbook10.5555/1882723.1882731(8-8)Online publication date: 1-Jan-2010
  • (2007)On the Complexity of Three-Dimensional Channel Routing (Extended Abstract)2007 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2007.378297(3399-3402)Online publication date: May-2007
  • (2007)Improvement of one‐dimensional module placement in VLSI layout designElectronics and Communications in Japan (Part III: Fundamental Electronic Science)10.1002/ecjc.443074070774:7(67-76)Online publication date: 21-Feb-2007
  • (2006)Finding a Maximum Planar Subset of a Set of Nets in a ChannelIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.1987.12702506:1(93-94)Online publication date: 1-Nov-2006
  • (2006)A Linear-Time Routing Algorithm for Convex GridsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.1985.12700994:1(68-76)Online publication date: 1-Nov-2006
  • (2006)Dogleg Channel Routing is NP-CompleteIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.1985.12700964:1(31-41)Online publication date: 1-Nov-2006
  • (2006)On river routing with minimum number of jogsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.6841510:2(271-273)Online publication date: 1-Nov-2006
  • (2006)An improved model for solving the optimal placement for river-routing problemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.25692112:10(1473-1480)Online publication date: 1-Nov-2006
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