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Building blocks for data flow prototypes

Published: 06 May 1980 Publication History

Abstract

A variety of proposed architectures for data flow computers have been advanced. Evaluation of the practical potential of these proposals is being studied through analysis and simulation, but these techniques cannot be used to study a machine design in sufficient detail to make accurate predictions of performance. As a basis for extrapolating cost/performance of these architectures, and for developing a methodology for data flow program preparation, the construction of prototype machines is needed. In this paper we present our plan for realizing experimental data flow machines as packet communication systems using two types of hardware elements: a microprogrammed processing element with provision for packet transmission and reception; and a router unit used to build networks to support packet communication among processing elements.

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  • (2005)Communication techniques in parallel processingParallel Computing in Science and Engineering10.1007/3-540-18923-8_14(35-60)Online publication date: 5-Jun-2005
  • (2005)Fine-grain parallel computing: The dataflow approachFuture Parallel Computers10.1007/3-540-18203-9_3(82-152)Online publication date: 28-May-2005
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cover image ACM Conferences
ISCA '80: Proceedings of the 7th annual symposium on Computer Architecture
May 1980
333 pages
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 06 May 1980

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Cited By

View all
  • (2010)A dynamic dataflow architecture using partial reconfigurable hardware as an option for multiple coresWSEAS Transactions on Computers10.5555/1852424.18524269:5(429-444)Online publication date: 1-May-2010
  • (2005)Communication techniques in parallel processingParallel Computing in Science and Engineering10.1007/3-540-18923-8_14(35-60)Online publication date: 5-Jun-2005
  • (2005)Fine-grain parallel computing: The dataflow approachFuture Parallel Computers10.1007/3-540-18203-9_3(82-152)Online publication date: 28-May-2005
  • (1996)A kind of Multistage Interconnection Networks with multiple pathsJournal of Computer Science and Technology10.1007/BF0294848311:4(395-404)Online publication date: Jul-1996
  • (1994)A History of Data-Flow LanguagesIEEE Annals of the History of Computing10.1109/85.32975716:4(38-59)Online publication date: 1-Dec-1994
  • (1989)Using the multistage cube network topology in parallel supercomputersProceedings of the IEEE10.1109/5.4883377:12(1932-1953)Online publication date: Jan-1989
  • (1988)A Prototyping Language for Real-Time SoftwareIEEE Transactions on Software Engineering10.1109/32.618614:10(1409-1423)Online publication date: 1-Oct-1988
  • (1988)Design and Analysis of Dynamic Redundancy NetworksIEEE Transactions on Computers10.1109/12.225337:9(1019-1029)Online publication date: 1-Sep-1988
  • (1988)Perspectives of data-flow architecturesAnnals of Operations Research10.1007/BF0228374916:1-4(281-297)Online publication date: 3-Jan-1988
  • (1988)Dataflow Architectures and Implicit Parallel ProgrammingMultiprocessing in Meteorological Models10.1007/978-3-642-83248-2_17(255-282)Online publication date: 1988
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