Article

Fractional-N frequency synthesizer design at the transfer function level using a direct closed loop realization algorithm

Authors:

Charlotte Y. Lau,

Michael H. PerrottAuthors Info & Claims

DAC '03: Proceedings of the 40th annual Design Automation Conference

Pages 526 - 531

https://doi.org/10.1145/775832.775966

Published: 02 June 2003 Publication History

Get Access

Abstract

A new methodology for designing fractional-N frequency synthesizers and other phase locked loop (PLL) circuits is presented. The approach achieves direct realization of the desired closed loop PLL transfer function given a set of user-specified parameters and automatically calculates the corresponding open loop PLL parameters. The algorithm also accomodates nonidealities such as parasitic poles and zeros. The entire methodology has been implemented in a GUI-based software package, which is used to verify the approach through comparison of the calculated and simulated dynamic and noise performance of a third order fractional-N frequency synthesizer.

References

[1]

F. M. Gardner. Phaselock Techniques. Wiley, New York, second edition, 1979.

Google Scholar

[2]

D. Johns and K. Martin. Analog Integrated Circuit Design. Wiley, 1997.

Google Scholar

[3]

T. Lee. The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge University Press, 1998.

Google Scholar

[4]

S. Mirabbasi and K. Martin. Design of Loop Filter in Phase-locked Loops. Electronics Letters, 35(21):1801--1802, Oct. 1999.

Google Scholar

[5]

M. Perrott. Fast and Accurate Behavioral Simulation of Fractional-N Frequency Synthesizers and other PLL/DLL Circuits. In Proceedings of Design Automation Conference, pages 498--503, June 2002.

Digital Library

Google Scholar

[6]

M. Perrott, M. Trott, and C. Sodini. A Modeling Approach for Fractional-N Frequency Synthesizers Allowing Straightforward Noise Analysis. IEEE Journal of Solid State Circuits, 37(8):1028--1038, Aug. 2002.

Crossref

Google Scholar

[7]

B. Razavi. Monolithic Phase-Locked Loops and Clock Recovery Circuits: Theory and Design. IEEE Press, New York, 1996.

Crossref

Google Scholar

[8]

T. A. Riley, M. A. Copeland, and T. A. Kwasniewski. Delta-Sigma Modulation in Fractional-N Frequency Synthesis. JSSC, 28(5):553--559, May 1993.

Google Scholar

Cited By

View all

Kurth PScholz PNickel PHecht UWittenhagen EMisselwitz KGerfers F(2024)A mmw Low-Noise Sub-Sampling Phase-Locked Loop with a Non-Pulsed Charge Pump, Frequency Calibration and a Compact Ultra-High-Q Resonator2024 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS58744.2024.10557980(1-5)Online publication date: 19-May-2024
https://doi.org/10.1109/ISCAS58744.2024.10557980
Bui LChau TLee J(2019)A low phase noise PLL using Vackar VCO and a wide-locking range tunable divider for V-band signal generation in 65-nm CMOSAnalog Integrated Circuits and Signal Processing10.1007/s10470-013-0075-176:1(91-102)Online publication date: 1-Jan-2019
https://dl.acm.org/doi/10.1007/s10470-013-0075-1
(2018)A 24 GHz dual FMCW radar to improve target detection for automotive radar applicationsInternational Journal of Information and Communication Technology10.1504/IJICT.2018.09056113:2(243-255)Online publication date: 19-Dec-2018
https://dl.acm.org/doi/10.1504/IJICT.2018.090561
Show More Cited By

Index Terms

Fractional-N frequency synthesizer design at the transfer function level using a direct closed loop realization algorithm
1. Computing methodologies
  1. Modeling and simulation

Recommendations

Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits
DAC '02: Proceedings of the 39th annual Design Automation Conference

Techniques for fast and accurate simulation of fractional-N synthesizers at a detailed behavioral level are presented. The techniques allow a uniform time step to be used for the simulator, and can be applied to a variety of phase locked loop (PLL) and ...
A fractional-N frequency synthesizer for single-chip UHF RFID reader

A novel fractional-N frequency synthesizer which is based on delta sigma modulator (DSM) and specialized for single-chip UHF 860-to-960 MHz band radio frequency identification (RFID) reader is proposed in this paper. The fractional-N synthesizer is ...
A 5-GHz CMOS frequency synthesizer with an injection-locked frequency divider and differential switched capacitors

A phase-locked loop (PLL)-based frequency synthesizer at 5 GHz is designed and fabricated in 0.18-µm CMOS technology. The power consumption of the synthesizer is significantly reduced by using an injection-locked frequency divider (ILFD) as the first ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

DAC '03: Proceedings of the 40th annual Design Automation Conference

June 2003

1014 pages

ISBN:1581136889

DOI:10.1145/775832

General Chair:
Ian Getreu
Ambric Inc., Portland, OR
,
Program Chairs:
Limor Fix
Intel Semiconductors Ltd., Haifa, Israel
,
Luciano Lavagno
Cadence Berkeley Labs., Berkeley, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 02 June 2003

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

DAC03

Sponsor:

SIGDA

DAC03: 2003 40th Annual Design Automation Conference

June 2 - 6, 2003

CA, Anaheim, USA

Acceptance Rates

DAC '03 Paper Acceptance Rate 152 of 628 submissions, 24%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

12
Total Citations
View Citations
675
Total Downloads

Downloads (Last 12 months)6
Downloads (Last 6 weeks)0

Reflects downloads up to 04 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Kurth PScholz PNickel PHecht UWittenhagen EMisselwitz KGerfers F(2024)A mmw Low-Noise Sub-Sampling Phase-Locked Loop with a Non-Pulsed Charge Pump, Frequency Calibration and a Compact Ultra-High-Q Resonator2024 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS58744.2024.10557980(1-5)Online publication date: 19-May-2024
https://doi.org/10.1109/ISCAS58744.2024.10557980
Bui LChau TLee J(2019)A low phase noise PLL using Vackar VCO and a wide-locking range tunable divider for V-band signal generation in 65-nm CMOSAnalog Integrated Circuits and Signal Processing10.1007/s10470-013-0075-176:1(91-102)Online publication date: 1-Jan-2019
https://dl.acm.org/doi/10.1007/s10470-013-0075-1
(2018)A 24 GHz dual FMCW radar to improve target detection for automotive radar applicationsInternational Journal of Information and Communication Technology10.1504/IJICT.2018.09056113:2(243-255)Online publication date: 19-Dec-2018
https://dl.acm.org/doi/10.1504/IJICT.2018.090561
Callegari SBizzarri FBrambilla A(2018)Optimal Coefficient Quantization in Optimal-NTF $\Delta \!\Sigma $ ModulatorsIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2018.282136865:5(542-546)Online publication date: May-2018
https://doi.org/10.1109/TCSII.2018.2821368
Hou BChen HWang ZMo JChen JYu FWang W(2017)A 11 mW 2.4 GHz 0.18 µm CMOS Transceivers for Wireless Sensor NetworksSensors10.3390/s1702022317:2(223)Online publication date: 24-Jan-2017
https://doi.org/10.3390/s17020223
Balcioglu YDundar G(2017)A standard cell phase locked loop design, analysis and high-level synthesis tool (CellPLL)Integration10.1016/j.vlsi.2017.04.00158(142-154)Online publication date: Jun-2017
https://doi.org/10.1016/j.vlsi.2017.04.001
Nguyen QHyonGi Yoo MyoungYeol Park Youngsu Kim Bien F(2015)A 77 GHz waveform generator with MFSK modulation for automotive radar applications2015 IEEE International Wireless Symposium (IWS 2015)10.1109/IEEE-IWS.2015.7164548(1-4)Online publication date: Mar-2015
https://doi.org/10.1109/IEEE-IWS.2015.7164548
Tan JLian Y(2009)A 1-volt, 2.5-mW, 2.4-GHz frequency synthesizer in 0.35-µm CMOS technology2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)10.1109/PRIMEASIA.2009.5397460(13-16)Online publication date: Nov-2009
https://doi.org/10.1109/PRIMEASIA.2009.5397460
Crain EPerrott M(2006)A 3.125 Gb/s Limit Amplifier in CMOS With 42 dB Gain and 1<tex>$mu$</tex>s Offset CompensationIEEE Journal of Solid-State Circuits10.1109/JSSC.2005.86235241:2(443-451)Online publication date: Feb-2006
https://doi.org/10.1109/JSSC.2005.862352
Rana R(2005)Programmable low-noise fast-settling fractional-N CMOS PLL with two control words for versatile applicationsIEE Proceedings - Circuits, Devices and Systems10.1049/ip-cds:20041237152:6(654)Online publication date: 2005
https://doi.org/10.1049/ip-cds:20041237
Show More Cited By

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits

A fractional-N frequency synthesizer for single-chip UHF RFID reader

A 5-GHz CMOS frequency synthesizer with an injection-locked frequency divider and differential switched capacitors