The present study introduces an unconventional and fast hybrid strategy for islanding detection in Distributed Generators (DGs) based on inverters. The active method utilized in this work is Sandia Frequency Shift (SFS), while the passive method ...

The global navigation satellite system (GNSS) spoofing technology is an important method to control the targets that pose threats and protect sensitive areas. Traction spoofing can gradually take over the tracking loop by spoofing signals. To ...

A technique to create a temperature insensitive area on a die using an integrated micro-heater and a phase-locked loop (PLL) configuration is described. The proposed PLL configuration employs thermal feedback through the micro-heater to ...

• A novel energy-based control is proposed for achieving leg and arm energy balance such that the components of the circulating currents responsible for ...

High Voltage Direct Current (HVDC) transmission has provided a variety of possibilities for renewable energy resources and regional substations to boost power supply reliability and operational flexibility. To accommodate this ...

Display Omitted

The presented work intends to encounter the challenge of optimizing frequency tracking in the C-band WLAN spectrum, with a tuning range and phase noise (PN) performance. A Quadrature Voltage Controlled Oscillator (QVCO) design in 130 nm CMOS ...

In order to solve the power consumption and cost problems caused by the massive nodes of the Internet of things chip, a new sub sampling PLL circuit is proposed in this paper. The circuit uses dynamic double loop technology to solve the harmonic locking ...

This paper presents a compact 0.0625–4 GHz fractional-N frequency synthesizer with quadrature phase output for software-defined radios (SDRs). Four voltage controlled oscillators (VCOs) and six cascaded dividers are used for wideband ...

This paper presents the complete design of a phase locked loop-based clock synthesizer for reconfigurable analog-to-digital converters. The synthesizer was implemented in TSMC 65 nm CMOS process technology and the presented results were obtained ...$$$$${}^{\mathrm{}}$$\mathrm{}\mathrm{}$

In this paper, we present a generic, high-throughput, and low-area true random number generator (TRNG) architecture based on synchronous edge sampling. Our approach exploits the entropy source from the jitter introduced by the clock generator with ...

This paper presents a wide frequency range three-stage voltage-controlled ring oscillator in CNTFET technology. The advantages of CNTFETs are the high speed of charge carriers, high signal to noise ratio, small size and ballistic transport. ...

In this paper, a CMOS mm-wave phase locked loop (PLL) with improved voltage controlled oscillator (VCO) and injection-locked frequency divider (ILFD) at operational harmonic frequency 125 GHz is presented. The VCO structure uses the bulk effective ...

This work presents a 1.6 GHz to 2 GHz integer PLL with 2 MHz stepping, which is optimized for driving low-power 180 nm switched-capacitor (SC) circuits at a 1.2 V supply. To reduce the overall power consumption, a class-F VCO is implemented. Due to ...

This paper presents a 922 MHz power-efficient configurable frequency-shift keying–on–off keying (FSK–OOK) phase-locked loop (PLL)-based transmitter. The proposed transmitter works as a multimode structure with configurable data rate and output ...

This paper proposes a new area-efficient, low-power and low-jitter phased-locked loop (PLL) architecture working off a low frequency reference. In this paper, new PLL is proposed with a new locking procedure with low complexity which results in ultra low ...

Understanding the biomechanical effects of cervical disc degeneration (CDD) on the cervical spine is fundamental for understanding the mechanisms of spinal disorders and improving clinical treatment. While the ...

• In this study, six degenerative cervical finite element models were developed based on clinical statistics data.

A fractional-N phase-locked loop (PLL) with four kinds of delta-sigma modulators (DSMs), is implemented to analyze and compare PLL phase noise and fractional spur performances among different DSMs, including 4^th- and 5^th-order single-loop (SL) and ...

In this paper, a robust carrier recovery loop for high dynamic and weak signals in GPS receivers is proposed. To achieve optimal tracking performance at synchronization loops, different methods are investigated. Since phase jitter sources are ...

One of the serious problems in the low earth orbit (LEO) satellite communication system is the very high Doppler frequency effect since the LEO satellite system runs very fast to keep the orbit altitude. Especially, this problem produces the ...

Most active noise control (ANC) algorithms require a model of the secondary path (SP). If there are large changes in the SP, online SP modeling algorithms may not be able to follow the changes quickly enough to prevent divergence. In this work, the ...