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Fast online/offline netlist compilation of hierarchical schematics

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L. G. JonesAuthors Info & Claims

DAC '89: Proceedings of the 26th ACM/IEEE Design Automation Conference

Pages 822 - 825

https://doi.org/10.1145/74382.74539

Published: 01 June 1989 Publication History

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Abstract

We present fast techniques for creating the netlist underlying a hierarchical schematic design. The methods can be used either for creating the netlist as a data structure for further online processing or for creating the netlist as a file for use with other offline design tools that are downstream from the compilation process. The methods we present have been used successfully in the implementation of a hierarchical schematic capture system that supports both netlist compilation and switch-level logic simulation.

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Cited By

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Jones L(2006)Fast batch incremental netlist compilation hierarchical schematicsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.8760210:7(922-931)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.87602
Jones L(2006)An incremental zero/integer delay switch-level simulation environmentIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.15999911:9(1131-1139)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.159999
Meyer S(1990)CAD tool interchangeability through Net list translationACM SIGDA Newsletter10.1145/378886.37889120:1(51-59)Online publication date: 1-Jun-1990
https://dl.acm.org/doi/10.1145/378886.378891
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Information

Published In

DAC '89: Proceedings of the 26th ACM/IEEE Design Automation Conference

June 1989

839 pages

ISBN:0897913108

DOI:10.1145/74382

Chairman:
Donald E. Thomas
Carnegie Mellon Univ., Pittsburgh, PA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 01 June 1989

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DAC89: The 26th ACM/IEEE-CS Design Automation Conference

June 25 - 28, 1989

Nevada, Las Vegas, USA

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DAC '89 Paper Acceptance Rate 156 of 465 submissions, 34%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Jones L(2006)Fast batch incremental netlist compilation hierarchical schematicsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.8760210:7(922-931)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.87602
Jones L(2006)An incremental zero/integer delay switch-level simulation environmentIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.15999911:9(1131-1139)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.159999
Meyer S(1990)CAD tool interchangeability through Net list translationACM SIGDA Newsletter10.1145/378886.37889120:1(51-59)Online publication date: 1-Jun-1990
https://dl.acm.org/doi/10.1145/378886.378891
Saab DThuns RBlaauw DRahmeh JAbraham J(1990)Hierarchical multi-level fault simulation of large systemsJournal of Electronic Testing: Theory and Applications10.1007/BF001373901:2(139-149)Online publication date: 1-Jun-1990
https://dl.acm.org/doi/10.1007/BF00137390
Jones L(1989)Fast incremental netlist compilation of hierarchical schematics1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers10.1109/ICCAD.1989.76963(326-329)Online publication date: 1989
https://doi.org/10.1109/ICCAD.1989.76963

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Fast batch incremental netlist compilation hierarchical schematics

Design of synchronous decimal counter using reversible Toffoli–Fredkin Netlist

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