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Multi-stack optimization for data-path chip (microprocessor) layout

Authors:

W. K. Luk,

A. A. DeanAuthors Info & Claims

DAC '89: Proceedings of the 26th ACM/IEEE Design Automation Conference

Pages 110 - 115

https://doi.org/10.1145/74382.74402

Published: 01 June 1989 Publication History

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Abstract

As data-path chips such as microprocessors and RISC chips become more complex, multiple stacks of data-path macros are required to implement the entire data-path. The physical decomposition of a chip into a single data-path stack, and control logic of random logic as in the past is not always feasible. This paper describes a special multi-stack structure, optimization techniques and algorithms to partition, place and wire the data-path macros in the form of the multi-stack structure, taking into account the connectivity of the entire chip logic (data-path, control logic, chip drivers, on-chip memory). The overall objective is: (1) to fit the circuits within the chip, (2) to ensure data-path wireability, including stack to random logic wireability, and (3) to minimize wire lengths for wireability and timing. A tool for automatic multi-stack optimization has been implemented and applied successfully to layout some high density data-path chips.

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Cited By

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Lin JDeng YLi SYu BChang LPeng T(2019)Regularity-Aware Routability-Driven Macro Placement Methodology for Mixed-Size Circuits With ObstaclesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.286783327:1(57-68)Online publication date: Jan-2019
https://doi.org/10.1109/TVLSI.2018.2867833
Chou SHsu MChang YGroeneveld PSciuto DHassoun S(2012)Structure-aware placement for datapath-intensive circuit designsProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228498(762-767)Online publication date: 3-Jun-2012
https://dl.acm.org/doi/10.1145/2228360.2228498
Wu AGajski D(2006)Partitioning algorithms for layout synthesis from register-transfer netlistsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.12509311:4(453-463)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.125093
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Index Terms

Multi-stack optimization for data-path chip (microprocessor) layout
1. Hardware

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Published In

DAC '89: Proceedings of the 26th ACM/IEEE Design Automation Conference

June 1989

839 pages

ISBN:0897913108

DOI:10.1145/74382

Chairman:
Donald E. Thomas
Carnegie Mellon Univ., Pittsburgh, PA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 1989

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IEEE-CS\TCDA
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DAC89: The 26th ACM/IEEE-CS Design Automation Conference

June 25 - 28, 1989

Nevada, Las Vegas, USA

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DAC '89 Paper Acceptance Rate 156 of 465 submissions, 34%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Lin JDeng YLi SYu BChang LPeng T(2019)Regularity-Aware Routability-Driven Macro Placement Methodology for Mixed-Size Circuits With ObstaclesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.286783327:1(57-68)Online publication date: Jan-2019
https://doi.org/10.1109/TVLSI.2018.2867833
Chou SHsu MChang YGroeneveld PSciuto DHassoun S(2012)Structure-aware placement for datapath-intensive circuit designsProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228498(762-767)Online publication date: 3-Jun-2012
https://dl.acm.org/doi/10.1145/2228360.2228498
Wu AGajski D(2006)Partitioning algorithms for layout synthesis from register-transfer netlistsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.12509311:4(453-463)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.125093
Frank ELengauer TRudell R(1995)APPlaUSEProceedings of the 1995 IEEE/ACM international conference on Computer-aided design10.5555/224841.225137(662-667)Online publication date: 1-Dec-1995
https://dl.acm.org/doi/10.5555/224841.225137
Frank OLengauer T(1995)APPlaUSE: area and performance optimization in a unified placement and synthesis environmentProceedings of IEEE International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD.1995.480200(662-667)Online publication date: 1995
https://doi.org/10.1109/ICCAD.1995.480200
Cheng CHo CLightner MJess J(1993)SEFOPProceedings of the 1993 IEEE/ACM international conference on Computer-aided design10.5555/259794.259824(178-181)Online publication date: 7-Nov-1993
https://dl.acm.org/doi/10.5555/259794.259824
Ramachandran CKurdahi FGajski DWu AChaiyakul VTrevillyan LLightner M(1992)Accurate layout area and delay modeling for system level designProceedings of the 1992 IEEE/ACM international conference on Computer-aided design10.5555/304032.304133(355-361)Online publication date: 8-Nov-1992
https://dl.acm.org/doi/10.5555/304032.304133
Ramachandran Kurdahi Gajski Wu Chaiyakul (1992)Accurate layout area and delay modeling for system level designIEEE/ACM International Conference on Computer-Aided Design10.1109/ICCAD.1992.279347(355-361)Online publication date: 1992
https://doi.org/10.1109/ICCAD.1992.279347
Wu CChen GGajski D(1990)Silicon compilation from register-transfer schematicsIEEE International Symposium on Circuits and Systems10.1109/ISCAS.1990.112535(2576-2579)Online publication date: 1990
https://doi.org/10.1109/ISCAS.1990.112535
Luk WDean AMathews J(1989)Multi-terrain partitioning and floor-planning for data-path chip (microprocessor) layout1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers10.1109/ICCAD.1989.76998(492-495)Online publication date: 1989
https://doi.org/10.1109/ICCAD.1989.76998

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Partitioning and floor-planning for data-path chip (microprocessor) layout

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Layout optimization and planning in deep sub-micron vlsi designs