Article

System level optimization and design space exploration for low power

Authors:

Arne SchulzAuthors Info & Claims

ISSS '01: Proceedings of the 14th international symposium on Systems synthesis

Pages 142 - 146

https://doi.org/10.1145/500001.500034

Published: 30 September 2001 Publication History

Get Access

Abstract

We present a software tool for power dissipation analysis and optimization on the algorithmic abstraction level from C/C++ and VHDL descriptions. An analysis is most efficient on such a high level since the influence of design decisions on the power demand increases with increasing abstraction [1]. The ORINOCO© tool enables to compare different but functionally equivalent algorithms and bindings to RT-level architectures with respect to power consumption. The results of the optimized binding can be used to guide synthesis. In the experimental evaluation we compare the predicted optimization trend with synthesized implementations and prove the accuracy of our methodology and tool.

References

[1]

A. Raghunathan, N.K. Niraj, S. Dey, "High-Level Power Analysis and Optimization", Kluwer Academic Publishers, 1998

Digital Library

Google Scholar

[2]

E. Macii, M. Pedram, F. Somenzi, "High Level Power Modeling, Estimation, and Optimization", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 17(11), pp. 1061 - 1079, November 1998

Digital Library

Google Scholar

[3]

G. Jochens, L. Kruse, E. Schmidt, W. Nebel, "A New Parameterizable Power Macro-Model for Datapath Components", in Proc. for DATE, pp. 29-36, 1999

Digital Library

Google Scholar

[4]

E. Schmidt, G. Jochens, L. Kruse, W. Nebel, "Automatic Nonlinear Memory Power Modelling", in Proc. for DATE, p. 808, 2001

Digital Library

Google Scholar

[5]

L. Kruse, E. Schmidt, G. Jochens, A. Stammermann, A. Schulz, E. Macii, and W. Nebel, "Estimation of Lower and Upper Bounds on the Power Consumption from Scheduled Data Flow Graphs", IEEE Transactions on Very Large Scale Integration (VLSI) Systems", pp. 3 - 14, February 2001

Digital Library

Google Scholar

[6]

L. Kruse, E. Schmidt, G. Jochens, A. Stammermann, W. Nebel, "Low Power Binding Heuristics", PATMOS-99, pp. 41-50, 1999

Google Scholar

[7]

A. Alvandpour, "Power Estimation and Low Power CMOS Circuit Techniques", Chapter 4, Link~ping Studies in Science and Technology, Dissertation Nr. 587, 1999

Google Scholar

[8]

A. Alvandpour, P. Larsson-Edefors, C. Svenssons, "GLMC: Interconnect Length Estimation by Growth-Limited Multifold Clustering", Proceedings of IEEE International Symposium on Circuits and Systems, pp. V 465-8, Geneva, Switzerland, 2000

Crossref

Google Scholar

[9]

A. Allara, M. Bombana, L. Kruse, E. Schmidt, A. Stammermann, "VHDL Behavioural Power Estimation for Telecom Devices", accepted at FDL, Lyon, September 2001

Google Scholar

[10]

N. Dutt and C. Ramachandran, Benchmarks for the 1992 high level synthesis workshop, Tech. Rep. #92-107, Dep. Inform. Comput. Sci., Univ. California, Irvine, 1992

Google Scholar

Cited By

View all

Spafford KVetter J(2015)Automated design space exploration with AspenScientific Programming10.1155/2015/1573052015(7-7)Online publication date: 1-Jan-2015
https://dl.acm.org/doi/10.1155/2015/157305
Guedes MAuler RBorin EAzevedo R(2012)An ArchC approach for automatic energy consumption characterization of processors2012 23rd IEEE International Symposium on Rapid System Prototyping (RSP)10.1109/RSP.2012.6380691(57-63)Online publication date: Oct-2012
https://doi.org/10.1109/RSP.2012.6380691
Chiou LChen YJian Y(2011)Energy-aware partitioning for on-chip bus architecture using a multi-objective genetic algorithmProceedings of 2011 International Symposium on VLSI Design, Automation and Test10.1109/VDAT.2011.5783544(1-4)Online publication date: Apr-2011
https://doi.org/10.1109/VDAT.2011.5783544
Show More Cited By

Index Terms

System level optimization and design space exploration for low power
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Very long instruction word
    2. Serial architectures
      1. Complex instruction set computing
      2. Reduced instruction set computing
2. Hardware
  1. Very large scale integration design
    1. Application-specific VLSI designs
      1. Application specific processors

Recommendations

Accelerating FPGA Prototyping through Predictive Model-Based HLS Design Space Exploration
DAC '19: Proceedings of the 56th Annual Design Automation Conference 2019

One of the advantages of High-Level Synthesis (HLS), also called C-based VLSI-design, over traditional RT-level VLSI design flows, is that multiple micro-architectures of unique area vs. performance can be automatically generated by setting different ...
Learning from the Past: Efficient High-level Synthesis Design Space Exploration for FPGAs
The quest to democratize the use of Field-Programmable Gate Arrays (FPGAs) has given High-Level Synthesis (HLS) the final push to be widely accepted with FPGA vendors strongly supporting this VLSI design methodology to expand the FPGA user base. HLS takes ...
SystemCoDesigner—an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications

With increasing design complexity, the gap from ESL (Electronic System Level) design to RTL synthesis becomes more and more crucial to many industrial projects. Although several behavioral synthesis tools exist to automatically generate synthesizable ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

ISSS '01: Proceedings of the 14th international symposium on Systems synthesis

September 2001

290 pages

ISBN:1581134185

DOI:10.1145/500001

General Chair:
Roman Hermida
Complutense Universidad, Madrid, Spain
,
Program Chair:
El Mostapha Aboulhamid
Université de Montréal, Québec, Canada

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 30 September 2001

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

ISSS01

Sponsor:

IEEE
SIGDA

ISSS01: 14th International Symposium on System Synthesis

September 30 - October 3, 2001

P.Q., Montréal, Canada

Acceptance Rates

Overall Acceptance Rate 38 of 71 submissions, 54%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

27
Total Citations
View Citations
398
Total Downloads

Downloads (Last 12 months)2
Downloads (Last 6 weeks)1

Reflects downloads up to 14 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Spafford KVetter J(2015)Automated design space exploration with AspenScientific Programming10.1155/2015/1573052015(7-7)Online publication date: 1-Jan-2015
https://dl.acm.org/doi/10.1155/2015/157305
Guedes MAuler RBorin EAzevedo R(2012)An ArchC approach for automatic energy consumption characterization of processors2012 23rd IEEE International Symposium on Rapid System Prototyping (RSP)10.1109/RSP.2012.6380691(57-63)Online publication date: Oct-2012
https://doi.org/10.1109/RSP.2012.6380691
Chiou LChen YJian Y(2011)Energy-aware partitioning for on-chip bus architecture using a multi-objective genetic algorithmProceedings of 2011 International Symposium on VLSI Design, Automation and Test10.1109/VDAT.2011.5783544(1-4)Online publication date: Apr-2011
https://doi.org/10.1109/VDAT.2011.5783544
Lawal NThornberg BO'Nils M(2011)Architecture driven memory allocation for FPGA based real-time video processing systems2011 VII Southern Conference on Programmable Logic (SPL)10.1109/SPL.2011.5782639(143-148)Online publication date: Apr-2011
https://doi.org/10.1109/SPL.2011.5782639
Wang ZXie XChen XLi X(2011)Design Considerations of Low‐Power Digital Integrated Systems for Implantable Medical ApplicationsCMOS Biomicrosystems10.1002/9781118016497.ch5(119-162)Online publication date: 3-May-2011
https://doi.org/10.1002/9781118016497.ch5
Lopes da Silva RGoncalves R(2010)D-PowerProceedings of the 2010 11th Symposium on Computing Systems10.1109/WSCAD-SCC.2010.21(56-63)Online publication date: 27-Oct-2010
https://dl.acm.org/doi/10.1109/WSCAD-SCC.2010.21
Helms DNebel WPiguet C(2009)High-Level Power Estimation and AnalysisLow-Power CMOS Circuits10.1201/9781420036503.ch18(1-25)Online publication date: 9-Nov-2009
https://doi.org/10.1201/9781420036503.ch18
Chen HLiu MHao WChen YJia CZhang CWang Z(2009)Low-Power Circuits for the Bidirectional Wireless Monitoring System of the Orthopedic ImplantsIEEE Transactions on Biomedical Circuits and Systems10.1109/TBCAS.2009.20262833:6(437-443)Online publication date: Dec-2009
https://doi.org/10.1109/TBCAS.2009.2026283
Hessel SSzczesny DTraboulsi SBilgic AHausner J(2009)On the Design of a Suitable Hardware Platform for Protocol Stack Processing in LTE TerminalsProceedings of the 2009 International Conference on Computational Science and Engineering - Volume 0210.1109/CSE.2009.37(1-8)Online publication date: 29-Aug-2009
https://dl.acm.org/doi/10.1109/CSE.2009.37
Mohanty SPrasanna V(2007)A model-based extensible framework for efficient application design using FPGAACM Transactions on Design Automation of Electronic Systems10.1145/1230800.123080512:2(13-es)Online publication date: 1-Apr-2007
https://dl.acm.org/doi/10.1145/1230800.1230805
Show More Cited By

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Accelerating FPGA Prototyping through Predictive Model-Based HLS Design Space Exploration

Learning from the Past: Efficient High-level Synthesis Design Space Exploration for FPGAs

SystemCoDesigner—an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications