Article

A sub-1V dual-threshold domino circuit using product-of-sum logic

Authors:

Koji Fujii,

Takakuni Douseki,

Yuichi KadoAuthors Info & Claims

ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and design

Pages 259 - 262

https://doi.org/10.1145/383082.383154

Published: 06 August 2001 Publication History

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References

[1]

T.Douseki,et.al.,"A 0.5 V SIMOX-MTCMOS Circuit with a 200-ps Logic Gate,"in ISSCC Dig.of Tech. Papers,pp.84-85,Feb.1996

Google Scholar

[2]

K.Fujii,et.al.,"A Sub-1 V Triple-Threshold CMOS/SIMOX Circuit for Active Power Reduction," in ISSCC Dig.Tech.Papers,pp.190-191,Feb.1998

Google Scholar

[3]

J.Kao and A.Chandrakasan,"Dual-Threshold Voltage Techniques for Low-Powe Digital Circuits, " IEEE J. Solid-State Circuits,vol.35,pp.1009-1018,Jul.1998

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Google Scholar

[4]

M.Allam,et.al.,"High-Speed Dynamic Logic Styles for Scaled-Down CMOS and MTCMOS Technologies " in Proc.of ISLPED,pp.155-160,Aug.2000

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Cited By

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Vasant SAngeline ABhaaskaran V(2016)Dual threshold HSCD domino adder structures2016 3rd International Conference on Devices, Circuits and Systems (ICDCS)10.1109/ICDCSyst.2016.7570606(267-271)Online publication date: Mar-2016
https://doi.org/10.1109/ICDCSyst.2016.7570606
Fu BYu QAmpadu PQu GIsmail YNarayanan VZhou H(2006)Energy-delay minimization in nanoscale domino logicProceedings of the 16th ACM Great Lakes symposium on VLSI10.1145/1127908.1127981(316-319)Online publication date: 30-Apr-2006
https://dl.acm.org/doi/10.1145/1127908.1127981
Bo Fu Ampadu P(2006)Techniques for Robust Energy Efficient Subthreshold Domino CMOS Circuits2006 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2006.1692818(1247-1250)Online publication date: 2006
https://doi.org/10.1109/ISCAS.2006.1692818
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A sub-1V dual-threshold domino circuit using product-of-sum logic
1. Hardware

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Published In

ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and design

August 2001

393 pages

ISBN:1581133715

DOI:10.1145/383082

Chairmen:
Enrico Macii
Politecnico di Torino, Turin, Italy
,
Vivek De
Intel Corporation, Hillsboro, OR
,
Mary Jane Irwin
Penn State Univ., University Park

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 06 August 2001

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ISLPED01

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SIGDA

ISLPED01: International Symposium on Low Power Electronics and Design

California, Huntington Beach, USA

Acceptance Rates

ISLPED '01 Paper Acceptance Rate 73 of 194 submissions, 38%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

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Vasant SAngeline ABhaaskaran V(2016)Dual threshold HSCD domino adder structures2016 3rd International Conference on Devices, Circuits and Systems (ICDCS)10.1109/ICDCSyst.2016.7570606(267-271)Online publication date: Mar-2016
https://doi.org/10.1109/ICDCSyst.2016.7570606
Fu BYu QAmpadu PQu GIsmail YNarayanan VZhou H(2006)Energy-delay minimization in nanoscale domino logicProceedings of the 16th ACM Great Lakes symposium on VLSI10.1145/1127908.1127981(316-319)Online publication date: 30-Apr-2006
https://dl.acm.org/doi/10.1145/1127908.1127981
Bo Fu Ampadu P(2006)Techniques for Robust Energy Efficient Subthreshold Domino CMOS Circuits2006 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2006.1692818(1247-1250)Online publication date: 2006
https://doi.org/10.1109/ISCAS.2006.1692818
Das KBrown R(2003)Ultra Low-Leakage Power Strategies for Sub-1 V VLSIProceedings of the 16th International Conference on VLSI Design10.5555/832285.835613Online publication date: 4-Jan-2003
https://dl.acm.org/doi/10.5555/832285.835613
Das KBrown R(2003)Ultra low-leakage power strategies for sub-1 V VLSI: novel circuit styles and design methodologies for partially depleted silicon-on-insulator (PD-SOI) CMOS technology16th International Conference on VLSI Design, 2003. Proceedings.10.1109/ICVD.2003.1183152(291-296)Online publication date: 2003
https://doi.org/10.1109/ICVD.2003.1183152

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Threshold logic circuit design of parallel adders using resonant tunneling devices