article

Speculative precomputation: long-range prefetching of delinquent loads

Authors:

Jamison D. Collins,

Dean M. Tullsen,

Christopher Hughes,

John P. ShenAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 29, Issue 2

Pages 14 - 25

https://doi.org/10.1145/384285.379248

Published: 01 May 2001 Publication History

Abstract

This paper explores Speculative Precomputation, a technique that uses idle thread context in a multithreaded architecture to improve performance of single-threaded applications. It attacks program stalls from data cache misses by pre-computing future memory accesses in available thread contexts, and prefetching these data. This technique is evaluated by simulating the performance of a research processor based on the Itanium™ ISA supporting Simultaneous Multithreading. Two primary forms of Speculative Precomputation are evaluated. If only the non-speculative thread spawns speculative threads, performance gains of up to 30% are achieved when assuming ideal hardware. However, this speedup drops considerably with more realistic hardware assumptions. Permitting speculative threads to directly spawn additional speculative threads reduces the overhead associated with spawning threads and enables significantly more aggressive speculation, overcoming this limitation. Even with realistic costs for spawning threads, speedups as high as 169% are achieved, with an average speedup of 76%.

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Cited By

Xue FHan CLi XWu JZhang TLiu THao YDu ZGuo QZhang F(2024)Tyche: An Efficient and General Prefetcher for Indirect Memory AccessesACM Transactions on Architecture and Code Optimization10.1145/364185321:2(1-26)Online publication date: 22-Jan-2024
https://dl.acm.org/doi/10.1145/3641853
Aly MChattopadhyay A(2022)Trends in Computing and Memory TechnologiesEmerging Computing: From Devices to Systems10.1007/978-981-16-7487-7_1(3-11)Online publication date: 9-Jul-2022
https://doi.org/10.1007/978-981-16-7487-7_1
Naithani AAinsworth SJones TEeckhout LMartínez JDuato JJohn L(2021)Vector runaheadProceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00024(195-208)Online publication date: 14-Jun-2021
https://dl.acm.org/doi/10.1109/ISCA52012.2021.00024
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Speculative precomputation: long-range prefetching of delinquent loads

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Information & Contributors

Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 29, Issue 2

Special Issue: Proceedings of the 28th annual international symposium on Computer architecture (ISCA '01)

May 2001

262 pages

ISSN:0163-5964

DOI:10.1145/384285

Editor:
Per Stenström
Chalmers Univ. of Technology

Issue’s Table of Contents

ISCA '01: Proceedings of the 28th annual international symposium on Computer architecture
June 2001
289 pages
ISBN:0769511627
DOI:10.1145/379240
Chairman:
Per Stenström
Chalmers Univ. of Technology

Copyright © 2001 Authors.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 May 2001

Published in SIGARCH Volume 29, Issue 2

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Cited By

Xue FHan CLi XWu JZhang TLiu THao YDu ZGuo QZhang F(2024)Tyche: An Efficient and General Prefetcher for Indirect Memory AccessesACM Transactions on Architecture and Code Optimization10.1145/364185321:2(1-26)Online publication date: 22-Jan-2024
https://dl.acm.org/doi/10.1145/3641853
Aly MChattopadhyay A(2022)Trends in Computing and Memory TechnologiesEmerging Computing: From Devices to Systems10.1007/978-981-16-7487-7_1(3-11)Online publication date: 9-Jul-2022
https://doi.org/10.1007/978-981-16-7487-7_1
Naithani AAinsworth SJones TEeckhout LMartínez JDuato JJohn L(2021)Vector runaheadProceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00024(195-208)Online publication date: 14-Jun-2021
https://dl.acm.org/doi/10.1109/ISCA52012.2021.00024
KAWAKAMI SONO TOHTSUKA TINOUE K(2018)Parallel Precomputation with Input Value Prediction for Model Predictive Control SystemsIEICE Transactions on Information and Systems10.1587/transinf.2018PAP0003E101.D:12(2864-2877)Online publication date: 1-Dec-2018
https://doi.org/10.1587/transinf.2018PAP0003
Yu XHughes CSatish NDevadas SPrvulovic M(2015)IMPProceedings of the 48th International Symposium on Microarchitecture10.1145/2830772.2830807(178-190)Online publication date: 5-Dec-2015
https://dl.acm.org/doi/10.1145/2830772.2830807
Góes LRibeiro CCastro MMéhaut JCole MCintra M(2014)Automatic Skeleton-Driven Memory Affinity for Transactional Worklist ApplicationsInternational Journal of Parallel Programming10.1007/s10766-013-0253-x42:2(365-382)Online publication date: 1-Apr-2014
https://dl.acm.org/doi/10.1007/s10766-013-0253-x
Nemirovsky MTullsen D(2013)Multithreading ArchitectureSynthesis Lectures on Computer Architecture10.2200/S00458ED1V01Y201212CAC0218:1(1-109)Online publication date: 15-Jan-2013
https://doi.org/10.2200/S00458ED1V01Y201212CAC021
Du YZhao YHan BLi Y(2010)Optimistic Parallelism Based on Speculative Asynchronous Messages PassingProceedings of the International Symposium on Parallel and Distributed Processing with Applications10.1109/ISPA.2010.43(382-391)Online publication date: 6-Sep-2010
https://dl.acm.org/doi/10.1109/ISPA.2010.43
Gao LLi LXue JNgai T(2009)Exploiting Speculative TLP in Recursive Programs by Dynamic Thread PredictionProceedings of the 18th International Conference on Compiler Construction: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 200910.1007/978-3-642-00722-4_7(78-93)Online publication date: 27-Mar-2009
https://dl.acm.org/doi/10.1007/978-3-642-00722-4_7
Chen TZhang TSura ZTallada MSoffa MDuesterwald E(2008)Prefetching irregular references for software cache on cellProceedings of the 6th annual IEEE/ACM international symposium on Code generation and optimization10.1145/1356058.1356079(155-164)Online publication date: 6-Apr-2008
https://dl.acm.org/doi/10.1145/1356058.1356079
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