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About this book
Multithreaded architectures now appear across the entire range of computing devices, from the highest-performing general purpose devices to low-end embedded processors. Multithreading enables a processor core to more effectively utilize its computational resources, as a stall in one thread need not cause execution resources to be idle. This enables the computer architect to maximize performance within area constraints, power constraints, or energy constraints. However, the architectural options for the processor designer or architect looking to implement multithreading are quite extensive and varied, as evidenced not only by the research literature but also by the variety of commercial implementations. This book introduces the basic concepts of multithreading, describes a number of models of multithreading, and then develops the three classic models (coarse-grain, fine-grain, and simultaneous multithreading) in greater detail. It describes a wide variety of architectural and software design tradeoffs, as well as opportunities specific to multithreading architectures. Finally, it details a number of important commercial and academic hardware implementations of multithreading. Table of Contents: Introduction / Multithreaded Execution Models / Coarse-Grain Multithreading / Fine-Grain Multithreading / Simultaneous Multithreading / Managing Contention / New Opportunities for Multithreaded Processors / Experimentation and Metrics / Implementations of Multithreaded Processors / Conclusion
Table of contents (9 chapters)
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Front Matter
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Back Matter
Authors and Affiliations
About the authors
Mario D. Nemirovsky is an ICREA Research Professor at the Barcelona Supercomputer Center, where he has been since 2007. He holds 62 patents and has authored over 30 research papers. Mario is a pioneer in multithreaded hardware-based processor architectures. During his tenure with the University of California, Santa Barbara, Mario co-authored some of the seminal works on simultaneous multithreading. Mario has made key contributions to other areas of computer architecture, including high performance, real-time, and network processors. He founded ConSentry Networks, Inc. where he served as CTO and VP Chief Scientist. He was the architect of ConSentry high performance processor (LSP-1) in which he pioneered the concept of Massively Multithreading (MMT). Earlier, Mario founded Flowstorm and XStream Logic, Inc. Before that, he was a chief architect at National Semiconductor, PI Researcher at Apple Computers, and Chief Architect at Weitek Inc. As chief architect at Delco Electronics, GeneralMotors (GM), he architected the GM multithread engine controller. He received his Ph.D. in ECE from University of California, Santa Barbara in 1990.Dean Tullsen is a Professor in the Computer Science and Engineering department at the University of California, San Diego, where he has been since 1996. He has authored over 90 research papers and hold 4 patents. In addition to co=authoring some of the seminal works on simultaneous multithreading, he and his co-authors have introduced many concepts to the research community, including speculative precomputation, symbiotic job scheduling, critical-path prediction, conjoined cores, single-ISA heterogeneous multicore architectures, balanced multithreading, and data-triggered threads. He received his B.S.and M.S.in computer engineering from UCLA, and his Ph.D.from University of Washington.He is a fellow of the IEEE and a fellow of the ACM. He has twice had papers selected for the International Symposium on Computer Architecture InfluentialPaper Award.
Bibliographic Information
Book Title: Multithreading Architecture
Authors: Mario Nemirovsky, Dean M. Tullsen
Series Title: Synthesis Lectures on Computer Architecture
DOI: https://doi.org/10.1007/978-3-031-01738-4
Publisher: Springer Cham
eBook Packages: Synthesis Collection of Technology (R0), eBColl Synthesis Collection 4
Copyright Information: Springer Nature Switzerland AG 2013
Softcover ISBN: 978-3-031-00610-4Published: 17 January 2013
eBook ISBN: 978-3-031-01738-4Published: 31 May 2022
Series ISSN: 1935-3235
Series E-ISSN: 1935-3243
Edition Number: 1
Number of Pages: XIV, 98