research-article

A single-source C++20 HLS flow for function evaluation on FPGA and beyond.

Authors:

Gauthier Harnisch,

Florent de DinechinAuthors Info & Claims

HEART '22: Proceedings of the 12th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies

Pages 51 - 58

https://doi.org/10.1145/3535044.3535051

Published: 09 June 2022 Publication History

Abstract

This paper presents a framework to reuse the intelligence of RTL generators in a single-source HLS setting. This framework is illustrated by a C++ fixed-point library to generate mathematical function evaluator. A compiler flow from C++20 to Vivado IPs has been developed to make the library usable with Vitis HLS. This flow is demonstrated on two applications: an adder for the logarithmic number system, and additive sound synthesis. These experiments show that the approach allows to easily tune the precision of the types used in the application. They also demonstrate the ability to generate arbitrary function evaluator at the required precision.

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Cited By

Rodriguez-Canal GBrown NDykes TJones JHaus U(2023)Fortran High-Level Synthesis: Reducing the Barriers to Accelerating HPC Codes on FPGAs2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL60245.2023.00010(10-18)Online publication date: 4-Sep-2023
https://doi.org/10.1109/FPL60245.2023.00010

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HEART '22: Proceedings of the 12th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies

June 2022

114 pages

ISBN:9781450396608

DOI:10.1145/3535044

Copyright © 2022 ACM.

Publication rights licensed to ACM. ACM acknowledges that this contribution was authored or co-authored by an employee, contractor or affiliate of a national government. As such, the Government retains a nonexclusive, royalty-free right to publish or reproduce this article, or to allow others to do so, for Government purposes only.

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Published: 09 June 2022

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HEART2022

HEART2022: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies

June 9 - 10, 2022

Tsukuba, Japan

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HEART '22 Paper Acceptance Rate 10 of 21 submissions, 48%;

Overall Acceptance Rate 22 of 50 submissions, 44%

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Cited By

Rodriguez-Canal GBrown NDykes TJones JHaus U(2023)Fortran High-Level Synthesis: Reducing the Barriers to Accelerating HPC Codes on FPGAs2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL60245.2023.00010(10-18)Online publication date: 4-Sep-2023
https://doi.org/10.1109/FPL60245.2023.00010

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