Article

Free access

Faster optimal single-row placement with fixed ordering

Authors:

U. Brenner,

J. VygenAuthors Info & Claims

DATE '00: Proceedings of the conference on Design, automation and test in Europe

Pages 117 - 121

https://doi.org/10.1145/343647.343716

Published: 01 January 2000 Publication History

PDF eReader Publisher Site

References

[1]

M.R. Garey, D.S. Johnson, L. Stockmeyer: Some Simplified NP-Complete Graph Problems. Theoretical Computer Science 1 (1976), 237-267

Crossref

Google Scholar

[2]

A.B. Kahng, P. Tucker, A. Zelikovsky: Optimization of Linear Placements for Wirelength Minimization with Free Sites. Proc. of the Asia and South Pacific Design Automation Conference, 1999, 241-244

Google Scholar

[3]

J. Vygen: Algorithms for Detailed Placement of Standard Cells. Proc. of the Conference Design, Automation and Test in Europe (DATE'98), IEEE 1998, 321- 324

Digital Library

Google Scholar

Cited By

View all

Hougardy SNeuwohner MSchorr U(2023)A Fast Optimal Double-row Legalization AlgorithmACM Transactions on Design Automation of Electronic Systems10.1145/357984428:5(1-26)Online publication date: 21-Jan-2023
https://dl.acm.org/doi/10.1145/3579844
Hougardy SNeuwohner MSchorr ULienig JBehjat LYang S(2021)A Fast Optimal Double Row Legalization AlgorithmProceedings of the 2021 International Symposium on Physical Design10.1145/3439706.3447044(23-30)Online publication date: 22-Mar-2021
https://dl.acm.org/doi/10.1145/3439706.3447044
Xiang HNam GTellez GRamji SXu XDi Natale GFummi F(2020)Self-aligned double-patterning aware legalizationProceedings of the 23rd Conference on Design, Automation and Test in Europe10.5555/3408352.3408613(1145-1150)Online publication date: 9-Mar-2020
https://dl.acm.org/doi/10.5555/3408352.3408613
Show More Cited By

Index Terms

Faster optimal single-row placement with fixed ordering
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

Recommendations

On legalization of row-based placements
GLSVLSI '04: Proceedings of the 14th ACM Great Lakes symposium on VLSI

Cell overlaps in the results of global placement are guaranteed to prevent successful routing. However, common techniques for fixing these problems may endanger routing in a different way --- through increased wirelength and congestion. We evaluate ...
Routability driven white space allocation for fixed-die standard-cell placement
ISPD '02: Proceedings of the 2002 international symposium on Physical design

The use of white space in fixed-die standard-cell placement is an effective way to improve routability. In this paper, we present a white space allocation approach that dynamically assigns white space according to the congestion distribution of the ...
On wirelength estimations for row-based placement

Wirelength estimation in very large scale integration layout is fundamental to any predetailed routing estimate of timing or routability. In this paper, we develop efficient wirelength estimation techniques appropriate for wirelength estimation during ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

DATE '00: Proceedings of the conference on Design, automation and test in Europe

January 2000

707 pages

ISBN:1581132441

DOI:10.1145/343647

Chairman:
Ivo Bolsens
IMEC, Leuven, Belgium

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 January 2000

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

DATE00

Sponsor:

EDAA
EDAC
SIGDA
IEEE-CS
IFIP
The Russian Academy of Sciences

DATE00: Design Automation and Test in Europe

March 27 - 30, 2000

Paris, France

Acceptance Rates

Overall Acceptance Rate 518 of 1,794 submissions, 29%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

36
Total Citations
View Citations
301
Total Downloads

Downloads (Last 12 months)29
Downloads (Last 6 weeks)6

Reflects downloads up to 28 Sep 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Hougardy SNeuwohner MSchorr U(2023)A Fast Optimal Double-row Legalization AlgorithmACM Transactions on Design Automation of Electronic Systems10.1145/357984428:5(1-26)Online publication date: 21-Jan-2023
https://dl.acm.org/doi/10.1145/3579844
Hougardy SNeuwohner MSchorr ULienig JBehjat LYang S(2021)A Fast Optimal Double Row Legalization AlgorithmProceedings of the 2021 International Symposium on Physical Design10.1145/3439706.3447044(23-30)Online publication date: 22-Mar-2021
https://dl.acm.org/doi/10.1145/3439706.3447044
Xiang HNam GTellez GRamji SXu XDi Natale GFummi F(2020)Self-aligned double-patterning aware legalizationProceedings of the 23rd Conference on Design, Automation and Test in Europe10.5555/3408352.3408613(1145-1150)Online publication date: 9-Mar-2020
https://dl.acm.org/doi/10.5555/3408352.3408613
Lin ZChang Y(2017)Detailed Placement for Two-Dimensional Directed Self-Assembly TechnologyProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062229(1-6)Online publication date: 18-Jun-2017
https://dl.acm.org/doi/10.1145/3061639.3062229
Ye WLin YXu XLi WFu YSun YZhan CPan D(2017)Placement mitigation techniques for power grid electromigration2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)10.1109/ISLPED.2017.8009178(1-6)Online publication date: Jul-2017
https://doi.org/10.1109/ISLPED.2017.8009178
Lin YYu BZou YLi ZAlpert CPan D(2017)Stitch aware detailed placement for multiple E-beam lithographyIntegration10.1016/j.vlsi.2017.02.00458(47-54)Online publication date: Jun-2017
https://doi.org/10.1016/j.vlsi.2017.02.004
Oikonomou PKoziri MDadaliaris AHatzaras YNerantzaki EStamoulis G(2016)Heuristics for Iterative Detailed Standard Cell PlacementProceedings of the SouthEast European Design Automation, Computer Engineering, Computer Networks and Social Media Conference10.1145/2984393.2984409(19-24)Online publication date: 25-Sep-2016
https://dl.acm.org/doi/10.1145/2984393.2984409
Yibo Lin Yu BYi Zou Li ZAlpert CPan D(2016)Stitch aware detailed placement for multiple e-beam lithography2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2016.7428009(186-191)Online publication date: Jan-2016
https://doi.org/10.1109/ASPDAC.2016.7428009
Yu BPan DYu BPan D(2016)Standard Cell Compliance and Placement Co-OptimizationDesign for Manufacturability with Advanced Lithography10.1007/978-3-319-20385-0_4(83-109)Online publication date: 2016
https://doi.org/10.1007/978-3-319-20385-0_4
Lin YYu BXu BPan DMarculescu DLiu F(2015)Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line ConflictProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840875(396-403)Online publication date: 2-Nov-2015
https://dl.acm.org/doi/10.5555/2840819.2840875
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

On legalization of row-based placements

Routability driven white space allocation for fixed-die standard-cell placement

On wirelength estimations for row-based placement