research-article

Public Access

Power Management of Monolithic 3D Manycore Chips with Inter-tier Process Variations

Authors:

Anwesha Chatterjee,

Shouvik Musavvir,

Janardhan Rao Doppa,

Partha Pratim PandeAuthors Info & Claims

ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 17, Issue 2

Article No.: 13, Pages 1 - 19

https://doi.org/10.1145/3430765

Published: 06 January 2021 Publication History

All formats PDF

Abstract

Voltage/frequency island (VFI)-based power management is a popular methodology for designing energy-efficient manycore architectures without incurring significant performance overhead. However, monolithic 3D (M3D) integration has emerged as an enabling technology to design high-performance and energy-efficient circuits and systems. The smaller dimension of vertical monolithic inter-tier vias (MIVs) lowers effective wirelength and allows high integration density. However, sequential fabrication of M3D layers introduces inter-tier process variations that affect the performance of transistors and interconnects in different layers. Therefore, VFI-based power management in M3D manycore systems requires the consideration of inter-tier process variation effects. In this work, we present the design of an imitation learning (IL)-enabled VFI-based power-management strategy that considers the inter-tier process-variation effects in M3D manycore chips. We demonstrate that the IL-based power-management strategy can be fine-tuned based on the M3D characteristics. Our policy generates suitable V/F levels based on the computation and communication characteristics of the system for both process-oblivious and process-aware configurations. We show that the proposed process-variation-aware IL-based VFI implementation for M3D manycore chips lowers the overall energy-delay-product (EDP) by up to 16.2% on average compared to an ideal M3D system with no M3D process variations.

References

[1]

W. R. Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A. M. Sule, M. Steer, and P. D. Franzon. 2005. Demystifying 3D ICs: The pros and cons of going vertical. IEEE Des. Test Comput. 22, 6 (2005), 498--510.

Digital Library

[2]

K. Sakuma, P. S. Andry, C. K. Tsang, S. L. Wright, B. Dang, C. S. Patel, B. C. Webb, J. Maria, E. J. Sprogis, S. K. Kang, and R. J. Polastre. 2008. 3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections. IBM J. Res. Dev. 52, 6 (2008), 611--622.

Digital Library

[3]

G. Van der Plas, P. Limaye, I. Loi, A. Mercha, H. Oprins, C. Torregiani, S. Thijs, D. Linten, M. Stucchi, G. Katti, and D. Velenis. 2010. Design issues and considerations for low-cost 3-D TSV IC technology. IEEE J. Solid-State Circ. 46, 1 (2010), 293--307.

[4]

H. H. S. Lee and K. Chakrabarty. 2009. Test challenges for 3D integrated circuits. IEEE Des. Test Comput. 26, 5 (2009), 26--35.

Digital Library

[5]

Y. J. Lee, D. Limbrick, and S. K. Lim. 2013. Power benefit study for ultra-high density transistor-level monolithic 3D ICs. In Proceedings of the Design Automation Conference (DAC’13). 1--10.

[6]

P. Batude, B. Sklenard, C. Fenouillet-Beranger, B. Previtali, C. Tabone, O. Rozeau, O. Billoint, O. Turkyilmaz, H. Sarhan, S. Thuries, G. Cibrario, L. Brunet, F. Deprat, J.-E. Michallet, F. Clermidy, and M. Vinet. 2014. 3D sequential integration opportunities and technology optimization. In Proceedings of the IEEE International Interconnect Technology Conference (IITC’14). 373--376.

[7]

D. K. Nayak, S. Banna, S. K. Samal, and S. K. Lim. 2015. Power, performance, and cost comparisons of monolithic 3D ICs and TSV-based 3D ICs. In Proceedings of the IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S’15). 1--2.

[8]

O. Turkyilmaz, G. Cibrario, O. Rozeau, P. Batude, and F. Clermidy. 2014. 3D FPGA using high-density interconnect monolithic integration. In Proceedings of the Conference on Design, Automation 8 Test in Europe (DATE’14). 1--4.

Digital Library

[9]

S. Das, J. R. Doppa, P. P. Pande, and K. Chakrabarty. 2017. Monolithic 3D-enabled high performance and energy efficient network-on-chip. In Proceedings of the IEEE International Conference on Computer Design (ICCD’17). 233--224.

[10]

B. Rajendran, R. S. Shenoy, D. J. Witte, N. S. Chokshi, R. L. DeLeon, G. S. Tompa, and R. F. W. Pease. 2007. Low thermal budget processing for sequential 3-D IC fabrication. IEEE Trans. Electron Dev. 54, 4 (2007), 707--714.

[11]

P. Batude, T. Ernst, J. Arcamone, G. Arndt, P. Coudrain, and P. Gaillardon. 2012. 3-D sequential integration: A key enabling technology for heterogeneous co-integration of new function with CMOS. IEEE J. Emerg. Select. Top. Circ. Syst. 2, 4 (2012), 714--722.

[12]

S. Musavvir, A. Chatterjee, R. G. Kim, D. H. Kim, and P. P. Pande. 2020. Inter-tier process-variation-aware monolithic 3-D NoC design space exploration. IEEE Trans. Very Large Scale Integ. (VLSI) Syst. 28, 3 (2020), 686--699.

Digital Library

[13]

D. Lee, S. Das, J. R. Doppa, P. P. Pande, and K. Chakrabarty. 2018. Performance and thermal tradeoffs for energy-efficient monolithic 3D network-on-chip. ACM Trans. Des. Autom. Electron. Syst. 23, 5 (2018), 1--25.

Digital Library

[14]

S. Bobba, A. Chakraborty, O. Thomas, P. Batude, and G. de Micheli. 2013. Cell transformations and physical design techniques for 3D monolithic integrated circuits. J. Emerg. Technol. Comput. Syst. 9, 3 (2013), 1--28.

Digital Library

[15]

M. Lin, A. El Gamal, Y. Lu, and S. Wong. 2007. Performance benefits of monolithically stacked 3-D FPGA. IEEE Trans. Comput.-Aided Des. Integ. Circ. Syst. 26, 2 (2007), 216--229.

Digital Library

[16]

T. Uhrmann, T. Wagenleitner, T. Glinsner, M. Wimplinger, and P. Lindner. 2014. Monolithic IC integration key alignment aspects for high process yield. In Proceedings of the SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S’14). 1--2.

[17]

Y. Lee and S. K. Lim. 2013. Ultrahigh density logic designs using monolithic 3-D integration. IEEE Trans. Comput.-Aided Des. Integ. Circ. Syst. 32, 12 (2013), 1892--1905.

Digital Library

[18]

Y. J. Lee, P. Morrow, and S. K. Lim. 2012. Ultra high density logic designs using transistor-level monolithic 3D integration. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD’12). 539--546.

[19]

S. K. Samal, D. Nayak, M. Ichihashi, S. Banna, and S. K. Lim. 2016. Monolithic 3D IC vs. TSV-based 3D IC in 14nm FinFET technology. In Proceedings of the IEEE SOI-3D-Subthreshold Microelectronic Technology Unified Conference (S3S’16). 1--2.

[20]

K. Acharya, K. Chang, B. W. Ku, S. Panth, S. Sinha, B. Cline, G. Yeric, and S. K. Lim. 2016. Monolithic 3D IC design: Power, performance, and area impact at 7nm. In Proceedings of the 17th International Symposium on Quality Electronic Design (ISQED’16). 41--48.

[21]

K. M. Kim, S. Sinha, B. Cline, G. Yeric, and S. K. Lim. 2016. Four-tier monolithic 3D ICs: Tier partitioning methodology and power benefit study. In Proceedings of the International Symposium on Low Power Electronics and Design. 70--75.

[22]

S. Panth, S. K. Samal, K. Samadi, Y. Du, and S. K. Lim. 2017. Tier degradation of monolithic 3-D ICs: A power performance study at different technology nodes. IEEE Trans. Comput.-Aided Des. Integ. Circ. Syst. 36, 8 (2017), 1265--1273.

Digital Library

[23]

L. Pasini, P. Batude, M. Cassé, L. Brunet, P. Rivallin, B. Mathieu, J. Lacord, S. Martinie, C. Fenouillet-Beranger, B. Previtali, N. Rambal, M. Haond, G. Ghibaudo, and M. Vinet. 2014. nFET FDSOI activated by low temperature solid phase epitaxial regrowth: Optimization guidelines. In Proceedings of the SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S’14). 1--2.

[24]

C. Fenouillet-Beranger, B. Mathieu, B. Previtali, M. Samson, N. Rambal, V. Benevent, S. Kerdiles, J. Barnes, D. Barge, P. Besson, R. Kachtouli, M. Cassé, X. Garros, A. Laurent, F. Nemouchi, K. Huet, I. Toqué-Trésonne, D. Lafond, H. Dansas, F. Aussenac, G. Druais, P. Perreau, E. Richard, S. Chhun, E. Petitprez, N. Guillot, F. Deprat, L. Pasini, L. Brunet, V. Lu, C. Reita, P. Batude, and M. Vinet. 2014. New insights on bottom layer thermal stability and laser annealing promises for high performance 3D VLSI. In Proceedings of the IEEE International Electron Device Meeting. 27, 5 (2014) 1--27.

[25]

B. Gopireddy and J. Torrellas. 2019. Designing vertical processors in monolithic 3D. In Proceedings of the 46th International Symposium on Computer Architecture (ISCA’19). Association for Computing Machinery, 643--656.

[26]

U. Y. Ogras, R. Marculescu, D. Marculescu, and E. G. Jung. 2009. Design and management of voltage-frequency island partitioned networks-on-chip. IEEE Trans. Very Large Scale Integ. Circ. Syst. 17 (2009), 330--341.

Digital Library

[27]

D. C. Juan, S. Garg, J. Park, and D. Marculescu. 2013. Learning the optimal operating point for many-core systems with extended range voltage/frequency scaling. In Proceedings of the IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS’13). 1--10.

Digital Library

[28]

R. G. Kim, W. Choi, Z. Chen, P. P. Pande, D. Marculescu, and R. Marculescu. 2016. Wireless NoC and Dynamic VFI codesign: Energy efficiency without performance penalty. IEEE Trans. Very Large Scale Integ. (VLSI) Syst. 24, 7 (2016), 2488--2501.

[29]

C. Ababei and M. G. Moghaddam. 2019. A survey of prediction and classification techniques in multicore processor systems. IEEE Trans. Parallel Distrib. Syst. 30, 5 (2019), 1184--1200.

[30]

R. G. Kim, W. Choi, Z. Chen, J. R. Doppa, P. P. Pande, D. Marculescu, and R. Marculescu. 2017. Imitation learning for dynamic VFI control in large-scale manycore systems. IEEE Trans. Very Large Scale Integ. (VLSI) Syst. 25, 9 (2017), 2458--2471.

Digital Library

[31]

M. M. Shulaker, T. F. Wu, M. M. Sabry, H. Wei, H. P. Wong, and S. Mitra. 2015. Monolithic 3D integration: A path from concept to reality. In Proceedings of the Design, Automation 8 Test in Europe Conference 8 Exhibition (DATE’15). 1197--1202.

[32]

K. Athikulwongse, A. Chakraborty, J.-S. Yang, D. Z. Pan, and S. K. Lim. 2010. Stress-driven 3D-IC placement with TSV keep-out zone and regularity study. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD’10). 669--674.

[33]

S. Ross, G. J. Gordon, and J. A. Bagnell. 2011. A reduction of imitation learning and structured prediction to no-regret online learning. In Proceedings of the International Conference on Artificial Intelligence and Statististics. 627--635.

[34]

N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D. R. Hower, T. Krishna, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M. D. Hill, and D. A. Wood. 2011. The gem5 simulator. SIGARCH Comput. Archit. News 39, 2 (2011), 1--7.

Digital Library

[35]

S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. 1995. The SPLASH-2 programs: Characterization and methodological considerations. In Proceedings of the International Symposium on Computer Architecture (ISCA’95). 24--36.

[36]

C. Bienia. 2011. Benchmarking Modern Multiprocessors. Ph.D. Dissertation. Princeton University, Princeton, NJ.

Digital Library

[37]

S. Li, J. H. Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen, and N. P. Jouppi. 2009. McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures. In Proceedings of the IEEE/ACM International Symposium on Microarchitecture (MICRO’09). 469--480.

[38]

S. Das, J. R. Doppa, P. P. Pande, and K. Chakrabarty. 2017. Robust TSV-based 3D NoC design to counteract electromigration and crosstalk noise. In Proceedings of the Design, Automation and Test in Europe Conference (DATE’17). 1366--1371.

[39]

S. Das, J. R. Doppa, P. P. Pande, and K. Chakrabarty. 2017. Design space exploration and optimization of an energy-efficient and reliable 3-D small-world network-on-chip. IEEE Trans. Comput.-Aided Des. Integ. Circ. Syst. 36, 5 (2017), 719--732.

Digital Library

[40]

J. Murray, N. Tang, P. P. Pande, D. Heo, and B. A. Shirazi. 2015. DVFS pruning for wireless NoC architectures. IEEE Trans. Des. Test 32, 2 (2015), 29--38.

[41]

S. Borkar. 2011. 3D integration for energy efficient system design. In Proceedings of the 48th Design Automation Conference (DAC’11). 214--219.

Digital Library

[42]

ITRS Reports. 2015. The International Technology Roadmap for Semiconductors. Retrieved from http://www.itrs2.net/itrs-reports.html.

[43]

F. Li, C. Nicopoulos, T. Richardson, Y. Xie, V. Narayanan, and M. Kandemir. 2006. Design and management of 3D chip multiprocessors using network-in-memory. In Proceedings of the IEEE International Symposium on Computer Architecture (ISCA’06). 130--141.

[44]

U. Kang, H. J. Chung, S. Heo, S. H. Ahn, H. Lee, S. H. Cha, J. Ahn, D. Kwon, J. H. Kim, J. W. Lee, H. S. Joo, W. S. Kim, H. K. Kim, E. M. Lee, S. R. Kim, K. H. Ma, D. H. Jang, N. S. Kim, M. S. Choi, S. J. Oh, J. B. Lee, T. K. Jung, J. H. Yoo, and C. Kim. 2009. 8Gb 3D DDR3 DRAM using through-silicon-via technology. In Proceedings of the IEEE International Solid-State Circuits Conference Digest of Technical Papers. 130--131.

[45]

M. Koyanagi, T. Nakamura, Y. Yamada, H. Kikuchi, T. Fukushima, T. Tanaka, and H. Kurino. 2006. Three-dimensional integration technology based on wafer bonding with vertical buried interconnections. IEEE Trans. Electron Dev. 53, 11 (2006), 2799--2808.

[46]

A. Rahmani, M. Haghbayan, A. Kanduri, A. Y. Weldezion, P. Liljeberg, J. Plosila, A. Jantsch, and H. Tenhunen. 2015. Dynamic power management for many-core platforms in the dark silicon era: A multi-objective control approach. In Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED’15). 219--224.

[47]

W. Sun, A. Venkatraman, G. J. Gordon, B. Boots, and J. A. Bagnell. 2017. Deeply AggreVaTeD: Differentiable imitation learning for sequential prediction. In Proceedings of the 34th International Conference Machine Learning 70 (2017), 3309--3318.

Cited By

Narang GDeshwal AAyoub RKishinevsky MRao Doppa JPande P(2023)Dynamic Power Management in Large Manycore Systems: A Learning-to-Search FrameworkACM Transactions on Design Automation of Electronic Systems10.1145/360350128:5(1-21)Online publication date: 6-Jun-2023
https://dl.acm.org/doi/10.1145/3603501
Do CKim CChung S(2023)Aggressive GPU cache bypassing with monolithic 3D-based NoCThe Journal of Supercomputing10.1007/s11227-022-04878-679:5(5421-5442)Online publication date: 1-Mar-2023
https://dl.acm.org/doi/10.1007/s11227-022-04878-6
Mirzaei MMohammadi S(2021)Low-power and variation-aware approximate arithmetic units for Image Processing ApplicationsAEU - International Journal of Electronics and Communications10.1016/j.aeue.2021.153825138(153825)Online publication date: Aug-2021
https://doi.org/10.1016/j.aeue.2021.153825

Index Terms

Power Management of Monolithic 3D Manycore Chips with Inter-tier Process Variations

Recommendations

Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip

Three-dimensional (3D) integration enables the design of high-performance and energy-efficient network on chip (NoC) architectures as communication backbones for manycore chips. To exploit the benefits of the vertical dimension of 3D integration, ...
Power benefit study for ultra-high density transistor-level monolithic 3D ICs
DAC '13: Proceedings of the 50th Annual Design Automation Conference

The nano-scale 3D interconnects available in monolithic 3D IC technology enable ultra-high density device integration at the individual transistor-level. In this paper we demonstrate the power benefits of transistor-level monolithic 3D designs. We first ...
Four-tier Monolithic 3D ICs: Tier Partitioning Methodology and Power Benefit Study
ISLPED '16: Proceedings of the 2016 International Symposium on Low Power Electronics and Design

Monolithic 3D IC is an emerging technology to continuously satisfy demands for power reduction under challenges posed by traditional device scaling. In this paper, for the first time, we study power benefits of 4-tier monolithic 3D ICs compared with 2-...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Journal on Emerging Technologies in Computing Systems

ACM Journal on Emerging Technologies in Computing Systems Volume 17, Issue 2

Hardware and Algorithms for Efficient Machine Learning

April 2021

360 pages

ISSN:1550-4832

EISSN:1550-4840

DOI:10.1145/3446841

Editor:
Ramesh Karri
Polytechnic Institute of New York University, USA

Issue’s Table of Contents

Copyright © 2021 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 06 January 2021

Accepted: 01 October 2020

Revised: 01 August 2020

Received: 01 May 2020

Published in JETC Volume 17, Issue 2

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed

Funding Sources

Army Research Office
NSF

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

3
Total Citations
View Citations
440
Total Downloads

Downloads (Last 12 months)131
Downloads (Last 6 weeks)16

Reflects downloads up to 02 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

Narang GDeshwal AAyoub RKishinevsky MRao Doppa JPande P(2023)Dynamic Power Management in Large Manycore Systems: A Learning-to-Search FrameworkACM Transactions on Design Automation of Electronic Systems10.1145/360350128:5(1-21)Online publication date: 6-Jun-2023
https://dl.acm.org/doi/10.1145/3603501
Do CKim CChung S(2023)Aggressive GPU cache bypassing with monolithic 3D-based NoCThe Journal of Supercomputing10.1007/s11227-022-04878-679:5(5421-5442)Online publication date: 1-Mar-2023
https://dl.acm.org/doi/10.1007/s11227-022-04878-6
Mirzaei MMohammadi S(2021)Low-power and variation-aware approximate arithmetic units for Image Processing ApplicationsAEU - International Journal of Electronics and Communications10.1016/j.aeue.2021.153825138(153825)Online publication date: Aug-2021
https://doi.org/10.1016/j.aeue.2021.153825

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

HTML Format

View this article in HTML Format.

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

Media

Figures

Other

Tables

View Issue’s Table of Contents