Cited By
View all- Marijan DZimmermann THam MSelic B(2021)Bridging Software Engineering Research and Industrial PracticeACM SIGSOFT Software Engineering Notes10.1145/3437479.343748846:1(30-32)Online publication date: 1-Feb-2021
Centralized Generic Interfaces in Hardware/Software Co-design for AI Accelerators
Pages 619 - 622
Abstract
A hardware/software co-design for AI accelerators such as Neural Processing Unit (NPU) is essential not only to support the required functionality but also to meet primary goals of improved performance and power efficiency. However, their ever-changing requirements often introduce undesirable development costs. Indeed, it is quite challenging for developers from different backgrounds to efficiently work together to construct a full HW/SW stack to develop AI accelerators.
This paper addresses these challenges, and proposes a centralized collaboration methodology for efficient full-stack development, especially targeting NPU HW. The proposal is inspired based on the observations from our experiences, presented later as a case study. As not all of the involved developers have enough knowledge of software engineering, this approach suggests making a central development group (e.g., runtime system software) have a higher priority to organize and devise common interfaces including APIs for each layer in the full-stack. This aims to minimize unnecessary discussions between development groups and hide any minor updates introduced with each new design, reducing the overall development costs and improving the quality of products. More importantly, each development group can focus on their work as much as possible with this approach.
References
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Computer Vision Foundation. 2019. CVPR 2019 Statistics. Retrieved Jan 21, 2020 from http://cvpr2019.thecvf.com/files/CVPR2019-WelcomeSlidesFinal.pdf
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Kaiyuan Guo, Song Han, Song Yao, Yu Wang, Yuan Xie, and Huazhong Yang. 2017. Software-Hardware Codesign for Efficient Neural Network Acceleration. IEEE Micro 2017 (2017).
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Andrey Ignatov, Radu Timofte, William Chou, Ke Wang, Max Wu, Tim Hartley, and Luc Van Gool. 2018. AI Benchmark: Running Deep Neural Networks on Android Smartphones. CoRR abs/1810.01109 (2018). arXiv:1810.01109
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Yu Ji, YouHui Zhang, ShuangChen Li, Ping Chi, CiHang Jiang, Peng Qu, Yuan Xie, and WenGuang Chen. 2016. NEUTRAMS: Neural network transformation and co-design under neuromorphic hardware constraints. In 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
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Sicheng Li, Wei Wen, Yu Wang, Song Han, Yiran Chen, and Hai Li. 2017. An FPGA Design Framework for CNN Sparsification and Acceleration. In IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines.
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Siqi Wang, Anuj Pathania, and Tulika Mitra. 2019. Neural Network Inference on Mobile SoCs. CoRR abs/1908.11450 (2019). arXiv:1908.11450
Index Terms
- Centralized Generic Interfaces in Hardware/Software Co-design for AI Accelerators
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Published In
June 2020
831 pages
ISBN:9781450379632
DOI:10.1145/3387940
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Published: 25 September 2020
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View all- Marijan DZimmermann THam MSelic B(2021)Bridging Software Engineering Research and Industrial PracticeACM SIGSOFT Software Engineering Notes10.1145/3437479.343748846:1(30-32)Online publication date: 1-Feb-2021
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