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Dual-Plane Switch Architecture for Time-Triggered Ethernet

Published: 07 September 2020 Publication History

Abstract

Time-triggered Ethernet (TTE) technology introduces the concept of time-triggered on the basis of traditional Ethernet, so that it can achieve conflict-free and deterministic service forwarding without sacrificing compatibility. However, storage resources in industrial, aviation, aerospace and other equipment are limited. Therefore, it is important for TTEthernet to develop switching technologies with high storage efficiency and scalability. This paper proposes a dual plane switching (DPS) architecture for TTEthernet, which divides time-triggered services and event-triggered services into two planes for data forwarding. Experimental results show that using the TTE switch of this architecture has the advantages of high clock synchronization accuracy, high throughout, low transmission delay and small jitter of TTE service.

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References

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Airlines Electronic Engineering Committee et al. 2002. Aircraft Data Network Part 7, Avionics Full Duplex Switched Ethernet (AFDX) Network, ARINC Specification 664. Aeronautical Radio(2002).
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Nick McKeown. 1999. The iSLIP scheduling algorithm for input-queued switches. IEEE/ACM transactions on networking 7, 2 (1999), 188--201.
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  • (2024)Design and implementation of a frame preemption model without guard bands for time-sensitive networkingComputer Networks10.1016/j.comnet.2024.110285243(110285)Online publication date: Apr-2024

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  1. Dual-Plane Switch Architecture for Time-Triggered Ethernet

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    GLSVLSI '20: Proceedings of the 2020 on Great Lakes Symposium on VLSI
    September 2020
    597 pages
    ISBN:9781450379441
    DOI:10.1145/3386263
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 07 September 2020

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    Author Tags

    1. dual plane switching architecture
    2. high throughout
    3. low transmission delay
    4. time-triggered ethernet

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    • Equipment Advance Research Aerospace Science and Technology Joint Fund

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    GLSVLSI '20
    GLSVLSI '20: Great Lakes Symposium on VLSI 2020
    September 7 - 9, 2020
    Virtual Event, China

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    Overall Acceptance Rate 312 of 1,156 submissions, 27%

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    • (2024)Design and implementation of a frame preemption model without guard bands for time-sensitive networkingComputer Networks10.1016/j.comnet.2024.110285243(110285)Online publication date: Apr-2024

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