Nothing Special   »   [go: up one dir, main page]

skip to main content
research-article

Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems

Published: 03 February 2020 Publication History

Abstract

<?tight?>To increase the resource utilization in multi-FPGA (field-programmable gate array) systems, time-division multiplexing (TDM) is a widely used technique to accommodate a large number of inter-FPGA signals. However, with this technique, the delay imposed by the inter-FPGA connections becomes significant. Previous research has shown that the TDM ratios of signals can greatly affect the performance of a system. In this article, to minimize the system clock period and support more practical constraints in modern multi-FPGA systems, we propose an analytical framework to optimize the TDM ratios of inter-FPGA nets. A Lagrangian relaxation-based method first gives a continuous result under relaxed constraints. A binary search--based discretization algorithm is then used to assign the TDM ratio of each net such that the resulting maximum displacement is optimal and all the constraints are satisfied. Finally, a swapping-based post refinement is performed to further optimize the TDM ratios. For comparison, we also solve the problem using linear programming (LP)--based methods, which have guaranteed error bounds to the optimal solutions. Experimental results show that our framework can achieve similar quality with much shorter runtime compared to the LP-based methods. Moreover, our framework scales for designs with over 45,000 inter-FPGA nets while the runtime and memory usage of the LP-based methods will increase dramatically as the design scale becomes larger.

References

[1]
Chak-Wa Pui and Evangeling F. Y. Young. 2019. Lagrangian relaxation-based time-division multiplexing optimization for multi-FPGA systems. In Proc. ICCAD.
[2]
Andrew Ling and Jason Anderson. 2017. The role of FPGAs in deep learning. In Proc. FPGA. 3--3.
[3]
George A. Constantinides. 2017. FPGAs in the cloud. In Proc. FPGA. 167--167.
[4]
Scott Hauck. 1998. The roles of FPGAs in reprogrammable systems. Proceedings of the IEEE 86, 4 (1998), 615--638.
[5]
Wan-Sin Kuo, Shi-Han Zhang, Wai-Kei Mak, Richard Sun, and Yoon Kah Leow. 2018. Pin assignment optimization for Multi-2.5 D FPGA-based systems. In Proceedings of the 2018 International Symposium on Physical Design. ACM, 106--113.
[6]
Jonathan Babb, Russell Tessier, Matthew Dahl, Silvina Zimi Hanono, David M. Hoki, and Anant Agarwal. 1997. Logic emulation with virtual wires. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 16, 6 (1997), 609--626.
[7]
William N. N. Hung and Richard Sun. 2018. Challenges in large FPGA-based logic emulation systems. In Proceedings of the 2018 International Symposium on Physical Design. ACM, 26--33.
[8]
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, and Atsushi Takahashi. 2008. Optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA prototyping systems. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 91, 12 (2008), 3539--3547.
[9]
Masato Inagi, Yasuhiro Takashima, and Yuichi Nakamura. 2009. Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems. In International Conference on Field Programmable Logic and Applications (FPL’09). IEEE, 212--217.
[10]
Masato Inagi, Yasuhiro Takashima, and Yuichi Nakamura. 2010. Globally optimal time-multiplexing of inter-FPGA connections for multi-FPGA prototyping systems. IPSJ Transactions on System LSI Design Methodology 3 (2010), 81--90.
[11]
Masato Inagi, Yuichi Nakamura, Yasuhiro Takashima, and Shin’ichi Wakabayashi. 2015. Inter-FPGA routing for partially time-multiplexing inter-FPGA signals on multi-FPGA systems with various topologies. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 98, 12 (2015), 2572--2583.
[12]
Shih-Chun Chen, Richard Sun, and Yao-Wen Chang. 2018. Simultaneous partitioning and signals grouping for time-division multiplexing in 2.5D FPGA-based systems. In Proc. ICCAD. 4.
[13]
Chak-Wa Pui, Gang Wu, Freddy Y. C. Mang, and Evangeling F. Y. Young. 2019. An analytical approach for time-division multiplexing optimization in multi-FPGA based systems. In Proc. SLIP.
[14]
Fung Yu Young, Chris C. N. Chu, W. S. Luk, and Y. C. Wong. 2000. Floorplan area minimization using Lagrangian relaxation. In Proceedings of the 2000 International Symposium on Physical Design. Citeseer, 174--179.
[15]
Chuan Lin, Hai Zhou, and Chris Chu. 2006. A revisit to floorplan optimization by Lagrangian relaxation. In Proceedings of the 2006 IEEE/ACM International Conference on Computer-Aided Design. ACM, 164--171.
[16]
Chung-Ping Chen, Chris C. N. Chu, and D. F. Wong. 1999. Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 18, 7 (1999), 1014--1025.
[17]
Hiran Tennakoon and Carl Sechen. 2002. Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step. In Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design. ACM, 395--402.
[18]
Jia Wang, Debasish Das, and Hai Zhou. 2009. Gate sizing by Lagrangian relaxation revisited. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 28, 7 (2009), 1071--1084.
[19]
Gang Wu and Chris Chu. 2017. Two approaches for timing-driven placement by Lagrangian relaxation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36, 12 (2017), 2093--2105.
[20]
Mohammed A. S. Khalid. 1999. Routing Architecture and Layout Synthesis for Multi-FPGA Systems. Ph. D. dissertation, Department of ECE, University of Toronto.
[21]
Mokhtar S. Bazaraa, Hanif D. Sherali, and Chitharanjan M. Shetty. 2013. Nonlinear Programming: Theory and Algorithms. John Wiley 8 Sons.
[22]
Stephen Yang, Aman Gayasen, Chandra Mulpuri, Sainath Reddy, and Rajat Aggarwal. 2016. Routability-driven FPGA placement contest. In Proc. ISPD. 139--143.
[23]
Ümit Çatalyürek and Cevdet Aykanat. 2011. Patoh (partitioning tool for hypergraphs). Encyclopedia of Parallel Computing (2011), 1479--1487.
[24]
Chak-Wa Pui, Gengjie Chen, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Peishan Tu, Hang Zhang, Evangeline F. Y. Young, and Bei Yu. 2016. RippleFPGA: A routability-driven placement for large-scale heterogeneous FPGAs. In Proc. ICCAD. 67:1--67:8.
[25]
Gengjie Chen, Chak-Wa Pui, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Evangeline F. Y. Young, and Bei Yu. 2018. RippleFPGA: Routability-driven simultaneous packing and placement for modern FPGAs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, 10 (Oct. 2018), 2022--2035.
[26]
Gurobi Optimization Inc. 2016. Gurobi Optimizer Reference Manual. Retrieved on 01 November, 2019 from http://www.gurobi.com.

Cited By

View all
  • (2024)A Method of Extracting and Visualizing Hierarchical Structure of Hardware Logic Based on Tree-Structure For FPGA-Based Prototyping2024 9th International Symposium on Computer and Information Processing Technology (ISCIPT)10.1109/ISCIPT61983.2024.10673222(554-561)Online publication date: 24-May-2024
  • (2024)Optimization of TDM Using Single-ended Transmission for Multi-FPGA Platforms2024 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS58744.2024.10558513(1-5)Online publication date: 19-May-2024
  • (2023)An Integrated Circuit Partitioning and TDM Assignment Optimization Framework for Multi-FPGA SystemsProceedings of the 28th Asia and South Pacific Design Automation Conference10.1145/3566097.3567897(522-528)Online publication date: 16-Jan-2023

Index Terms

  1. Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems

      Recommendations

      Comments

      Please enable JavaScript to view thecomments powered by Disqus.

      Information & Contributors

      Information

      Published In

      cover image ACM Transactions on Design Automation of Electronic Systems
      ACM Transactions on Design Automation of Electronic Systems  Volume 25, Issue 2
      March 2020
      256 pages
      ISSN:1084-4309
      EISSN:1557-7309
      DOI:10.1145/3375457
      • Editor:
      • Naehyuck Chang
      Issue’s Table of Contents
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Journal Family

      Publication History

      Published: 03 February 2020
      Accepted: 01 December 2019
      Revised: 01 October 2019
      Received: 01 July 2019
      Published in TODAES Volume 25, Issue 2

      Permissions

      Request permissions for this article.

      Check for updates

      Author Tags

      1. EDA
      2. FPGA
      3. Lagrangian relaxation
      4. routing
      5. time-division multiplexing

      Qualifiers

      • Research-article
      • Research
      • Refereed

      Funding Sources

      • Research Grants Council of the Hong Kong Special Administrative Region, China

      Contributors

      Other Metrics

      Bibliometrics & Citations

      Bibliometrics

      Article Metrics

      • Downloads (Last 12 months)28
      • Downloads (Last 6 weeks)4
      Reflects downloads up to 09 Nov 2024

      Other Metrics

      Citations

      Cited By

      View all
      • (2024)A Method of Extracting and Visualizing Hierarchical Structure of Hardware Logic Based on Tree-Structure For FPGA-Based Prototyping2024 9th International Symposium on Computer and Information Processing Technology (ISCIPT)10.1109/ISCIPT61983.2024.10673222(554-561)Online publication date: 24-May-2024
      • (2024)Optimization of TDM Using Single-ended Transmission for Multi-FPGA Platforms2024 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS58744.2024.10558513(1-5)Online publication date: 19-May-2024
      • (2023)An Integrated Circuit Partitioning and TDM Assignment Optimization Framework for Multi-FPGA SystemsProceedings of the 28th Asia and South Pacific Design Automation Conference10.1145/3566097.3567897(522-528)Online publication date: 16-Jan-2023
      • (2021)ALIFRouter: A Practical Architecture-Level Inter-FPGA Router for Logic Verification2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE51398.2021.9474255(1570-1573)Online publication date: 1-Feb-2021

      View Options

      Get Access

      Login options

      Full Access

      View options

      PDF

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader

      HTML Format

      View this article in HTML Format.

      HTML Format

      Media

      Figures

      Other

      Tables

      Share

      Share

      Share this Publication link

      Share on social media