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Output-based Intermediate Representation for Translation of Test-pattern Program

Published: 07 October 2019 Publication History

Abstract

An Intermediate Representation (IR) used by compilers is normally generated statically, as a result of parsing or analyzing the source program. This paper proposes a completely different type of IR, generated as a result of running the source program, the output-based IR. There is a practical translation problem where such an IR is useful, in the domain of test-pattern programs.
Test-pattern programs run on ATE (automatic test equipment), a special embedded system to test semiconductors such as DRAMs. They generate a pattern for each clock, a bit vector input to the pins of the chip. One issue is that different ATEs require different programming since each ATE manufacturer has its own programming language. Nonetheless, we should be able to test a memory chip on different ATEs as long as they generate the same patterns with the same speed. Therefore, a memory chipmaker wants to make a pattern program portable across ATEs, to fully utilize their ATE resources.
One solution is translating between pattern programs, for which we need an IR since there are multiple source ATEs and target ATEs. Instead of a conventional, static IR, we propose using the output pattern itself as an IR. Since the pattern is independent of ATEs and easily obtainable, the output-based IR obviates designing a static IR considering all ATE programming languages and hardware differences. Moreover, we might synthesize a better target program from the IR, more optimized to the target ATE. However, the full pattern generated by a product-level pattern program is huge, so we propose using an IR of abbreviated patterns, annotated with the repetition information obtained while executing the source program. Our experimental results with product-level pattern programs show that our approach is feasible.

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Cited By

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  • (2022)Solving PBQP-based register allocation using deep reinforcement learningProceedings of the 20th IEEE/ACM International Symposium on Code Generation and Optimization10.1109/CGO53902.2022.9741272(230-241)Online publication date: 2-Apr-2022
  • (2020)Irregular Register Allocation for Translation of Test-pattern ProgramsACM Transactions on Architecture and Code Optimization10.1145/342737818:1(1-23)Online publication date: 30-Dec-2020

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Published In

cover image ACM Transactions on Embedded Computing Systems
ACM Transactions on Embedded Computing Systems  Volume 18, Issue 5s
Special Issue ESWEEK 2019, CASES 2019, CODES+ISSS 2019 and EMSOFT 2019
October 2019
1423 pages
ISSN:1539-9087
EISSN:1558-3465
DOI:10.1145/3365919
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 07 October 2019
Accepted: 01 July 2019
Revised: 01 June 2019
Received: 01 April 2019
Published in TECS Volume 18, Issue 5s

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Author Tags

  1. Intermediate representation
  2. automatic test equipment
  3. domain-specific language
  4. test-pattern program
  5. translation

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View all
  • (2022)Solving PBQP-based register allocation using deep reinforcement learningProceedings of the 20th IEEE/ACM International Symposium on Code Generation and Optimization10.1109/CGO53902.2022.9741272(230-241)Online publication date: 2-Apr-2022
  • (2020)Irregular Register Allocation for Translation of Test-pattern ProgramsACM Transactions on Architecture and Code Optimization10.1145/342737818:1(1-23)Online publication date: 30-Dec-2020

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