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Rethinking cycle accurate DRAM simulation

Published: 30 September 2019 Publication History

Abstract

Cycle accurate DRAM simulations have been the dominating architecture simulation model for DRAM for a long time. Although accurate, its poor simulation speed has not improved for years while a lot of other architecture simulators such as CPU and cache simulators have moved away from cycle-accurate models for better performance. In this paper, we discuss limitations of cycle-accurate DRAM models, through simulation experiments, we show that cycle-accurate DRAM simulator is becoming a dominant part of overall simulation time when paired with modern CPU simulators. We also demonstrate the inherent inflexibility of cycle-accurate models becomes the roadblock for faster simulation speed and integration with other non-cycle-accurate simulation frameworks. Finally, we discuss alternative modeling techniques for DRAM simulation and point out potential pathways to further DRAM simulation technique.

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Cited By

View all
  • (2024)SEFsim: A Statistically-Guided Fast DRAM Simulator2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)10.1109/ISPASS61541.2024.00039(304-306)Online publication date: 5-May-2024
  • (2023)A survey of software techniques to emulate heterogeneous memory systems in high-performance computingParallel Computing10.1016/j.parco.2023.103023116:COnline publication date: 1-Jul-2023
  • (2022)DRAMSys4.0: An Open-Source Simulation Framework for In-depth DRAM AnalysesInternational Journal of Parallel Programming10.1007/s10766-022-00727-450:2(217-242)Online publication date: 12-Mar-2022
  • Show More Cited By

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cover image ACM Other conferences
MEMSYS '19: Proceedings of the International Symposium on Memory Systems
September 2019
517 pages
ISBN:9781450372060
DOI:10.1145/3357526
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 30 September 2019

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Author Tags

  1. DRAM modeling
  2. architecture simulation
  3. cycle accurate simulation

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MEMSYS '19
MEMSYS '19: The International Symposium on Memory Systems
September 30 - October 3, 2019
District of Columbia, Washington, USA

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Cited By

View all
  • (2024)SEFsim: A Statistically-Guided Fast DRAM Simulator2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)10.1109/ISPASS61541.2024.00039(304-306)Online publication date: 5-May-2024
  • (2023)A survey of software techniques to emulate heterogeneous memory systems in high-performance computingParallel Computing10.1016/j.parco.2023.103023116:COnline publication date: 1-Jul-2023
  • (2022)DRAMSys4.0: An Open-Source Simulation Framework for In-depth DRAM AnalysesInternational Journal of Parallel Programming10.1007/s10766-022-00727-450:2(217-242)Online publication date: 12-Mar-2022
  • (2021)Taming the zooProceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00041(429-442)Online publication date: 14-Jun-2021
  • (2020)MCsim: An Extensible DRAM Memory Controller SimulatorIEEE Computer Architecture Letters10.1109/LCA.2020.300828819:2(105-109)Online publication date: 1-Jul-2020
  • (2020)DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM SimulatorEmbedded Computer Systems: Architectures, Modeling, and Simulation10.1007/978-3-030-60939-9_8(110-126)Online publication date: 7-Oct-2020

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