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Test Routines Based on Symbolic Logical Statements

Author:

Richard D. EldredAuthors Info & Claims

Journal of the ACM (JACM), Volume 6, Issue 1

Pages 33 - 37

https://doi.org/10.1145/320954.320957

Published: 01 January 1959 Publication History

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Petrolo VMedya SGraziano MPal D(2024)DETECTive: Machine Learning-driven Automatic Test Pattern Prediction for Faults in Digital CircuitsProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3658696(32-37)Online publication date: 12-Jun-2024
https://dl.acm.org/doi/10.1145/3649476.3658696
Zhao HYang FShan J(2024)A Graph AutoEncoder Approach for Fault Prediction in Test Pattern Generation2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10618040(462-467)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10618040
Busbait MMoshkov MMoshkova AShevtchenko VBusbait MMoshkov MMoshkova AShevtchenko V(2023)IntroductionDecision Trees for Fault Diagnosis in Circuits and Switching Networks10.1007/978-3-031-39031-9_1(1-11)Online publication date: 11-Aug-2023
https://doi.org/10.1007/978-3-031-39031-9_1
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Index Terms

Test Routines Based on Symbolic Logical Statements
1. Software and its engineering
  1. Software creation and management
    1. Software verification and validation
      1. Software defect analysis
        Software testing and debugging
2. Theory of computation
  1. Logic
    1. Constraint and logic programming

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Information

Published In

Journal of the ACM Volume 6, Issue 1

Jan. 1959

114 pages

ISSN:0004-5411

EISSN:1557-735X

DOI:10.1145/320954

Issue’s Table of Contents

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 January 1959

Published in JACM Volume 6, Issue 1

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Petrolo VMedya SGraziano MPal D(2024)DETECTive: Machine Learning-driven Automatic Test Pattern Prediction for Faults in Digital CircuitsProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3658696(32-37)Online publication date: 12-Jun-2024
https://dl.acm.org/doi/10.1145/3649476.3658696
Zhao HYang FShan J(2024)A Graph AutoEncoder Approach for Fault Prediction in Test Pattern Generation2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10618040(462-467)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10618040
Busbait MMoshkov MMoshkova AShevtchenko VBusbait MMoshkov MMoshkova AShevtchenko V(2023)IntroductionDecision Trees for Fault Diagnosis in Circuits and Switching Networks10.1007/978-3-031-39031-9_1(1-11)Online publication date: 11-Aug-2023
https://doi.org/10.1007/978-3-031-39031-9_1
Chen HWen XCheng W(2023)Prerequisites on Fault DiagnosisMachine Learning Support for Fault Diagnosis of System-on-Chip10.1007/978-3-031-19639-3_1(1-24)Online publication date: 14-Mar-2023
https://doi.org/10.1007/978-3-031-19639-3_1
Sanchez-Diaz GLazo-Cortes MAguirre-Salado CPiza-Davila IGarcia-Contreras J(2022)A review of algorithms to computing irreducible testors applied to feature selectionArtificial Intelligence Review10.1007/s10462-022-10162-z55:8(6607-6628)Online publication date: 1-Dec-2022
https://dl.acm.org/doi/10.1007/s10462-022-10162-z
Traiola MDeveautour BBosio AGirard PVirazel A(2022)Test and Reliability of Approximate HardwareApproximate Computing10.1007/978-3-030-98347-5_10(233-266)Online publication date: 18-Mar-2022
https://doi.org/10.1007/978-3-030-98347-5_10
Bosio ACarlo SGirard PRuospo ASanchez ESavino ASekanina LTraiola MVasicek ZVirazel A(2022)Design, Verification, Test, and In-Field Implications of Approximate Digital Integrated CircuitsApproximate Computing Techniques10.1007/978-3-030-94705-7_12(349-385)Online publication date: 3-Jan-2022
https://doi.org/10.1007/978-3-030-94705-7_12
Gao ZHu MMalagi SSwenton JHuisken JGoossens KMarinissen E(2021)Reducing Library Characterization Time for Cell-aware Test while Maintaining Test QualityJournal of Electronic Testing: Theory and Applications10.1007/s10836-021-05943-337:2(161-189)Online publication date: 1-Apr-2021
https://dl.acm.org/doi/10.1007/s10836-021-05943-3
Huhn SDrechsler RHuhn SDrechsler R(2021)Integrated CircuitsDesign for Testability, Debug and Reliability10.1007/978-3-030-69209-4_2(9-31)Online publication date: 27-Jan-2021
https://doi.org/10.1007/978-3-030-69209-4_2
Huhn SDrechsler RHuhn SDrechsler R(2021)IntroductionDesign for Testability, Debug and Reliability10.1007/978-3-030-69209-4_1(1-6)Online publication date: 27-Jan-2021
https://doi.org/10.1007/978-3-030-69209-4_1
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