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Abstract

For several years, the design and fabrication of ICs no longer aim at producing devices, which fulfill one dedicated task. Instead, highly complex application scenarios are targeted, which require several heterogeneous functions to be jointly implemented on-chip at once. For this purpose, SoC designs have been successfully designed, which hold several nested modules, which inevitably lead to increasing complexity in the sense of transistor count. One important step towards this is the on-going reduction of the feature size of the used technology node, which implies that a single transistor is heavily shrunk.

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Huhn, S., Drechsler, R. (2021). Introduction. In: Design for Testability, Debug and Reliability. Springer, Cham. https://doi.org/10.1007/978-3-030-69209-4_1

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  • DOI: https://doi.org/10.1007/978-3-030-69209-4_1

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