FAL-based High Reusability and Automated Verification Platform
Article No.: 58, Pages 1 - 5
Abstract
With1 the continuous improvement of the complexity and integration of integrated circuits, verification work is consuming more and more time. The generation of test vector and the automation and reusability of verification platform are the key factors to improve verification efficiency. In this paper, we propose a modeling tool named FALMT. FALMT can not only model the function point of the design based on FAL, but also can complete the function of automatically generating the high reusability verification platform. In this way, the generation of the test vector and the verification platform does not require too much human intervention. Experiments show that the proposed methodology can shorten the verification cycle and speed up the verification process, shortening the time by 46.6%.
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Index Terms
- FAL-based High Reusability and Automated Verification Platform
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October 2018
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Association for Computing Machinery
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Published: 22 October 2018
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CSAE '18
CSAE '18: The 2nd International Conference on Computer Science and Application Engineering
October 22 - 24, 2018
Hohhot, China
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CSAE '18 Paper Acceptance Rate 189 of 383 submissions, 49%;
Overall Acceptance Rate 368 of 770 submissions, 48%
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