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- Sun YYuan YYu ZKuper RSong CHuang JJi HAgarwal SLou JJeong IWang RAhn JXu TKim N(2023)Demystifying CXL Memory with Genuine CXL-Ready Systems and DevicesProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3614256(105-121)Online publication date: 28-Oct-2023
- Lee HLee SJung YKim D(2023)T-CAT: Dynamic Cache Allocation for Tiered Memory Systems With Memory InterleavingIEEE Computer Architecture Letters10.1109/LCA.2023.329019722:2(73-76)Online publication date: Jul-2023
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