research-article

Customized Locking of IP Blocks on a Multi-Million-Gate SoC

Authors:

Abhrajit Sengupta,

Mohammed Ashraf,

Mohammed Nabeel,

Ozgur SinanogluAuthors Info & Claims

2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Pages 1 - 7

https://doi.org/10.1145/3240765.3243467

Published: 05 November 2018 Publication History

Abstract

Reliance on off-site untrusted fabrication facilities has given rise to several threats such as intellectual property (IP) piracy, overbuilding and hardware Trojans. Logic locking is a promising defense technique against such malicious activities that is effected at the silicon layer. Over the past decade, several logic locking defenses and attacks have been presented, thereby, enhancing the state-of-the-art. Nevertheless, there has been little research aiming to demonstrate the applicability of logic locking with large-scale multi-million-gate industrial designs consisting of multiple IP blocks with different security requirements. In this work, we take on this challenge to successfully lock a multi-million-gate system-on-chip (SoC) provided by DARPA by taking it all the way to GDSII layout. We analyze how specific features, constraints, and security requirements of an IP block can be leveraged to lock its functionality in the most appropriate way. We show that the blocks of an SoC can be locked in a customized manner at 0.5%, 15.3%, and 1.5% chip-level overhead in power, performance, and area, respectively.

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Cited By

Dasgupta AParia SChakraborty PBhunia S(2024)Splitting the Secrets: A Cooperative Trust Model for System-on-Chip Designs with Untrusted IPs2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI61997.2024.00066(325-330)Online publication date: 1-Jul-2024
https://doi.org/10.1109/ISVLSI61997.2024.00066
Pilato CCollini LCassano LSciuto DGarg SKarri R(2023)Optimizing the Use of Behavioral Locking for High-Level SynthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.317965142:2(462-472)Online publication date: Feb-2023
https://doi.org/10.1109/TCAD.2022.3179651
Supon TRashidzadeh R(2023)Hardware Trojan prevention using memristor technologyMicroprocessors & Microsystems10.1016/j.micpro.2023.104915102:COnline publication date: 1-Oct-2023
https://dl.acm.org/doi/10.1016/j.micpro.2023.104915
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cover image Guide Proceedings

2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Nov 2018

939 pages

Copyright © 2018.

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IEEE Press

Publication History

Published: 05 November 2018

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Cited By

Dasgupta AParia SChakraborty PBhunia S(2024)Splitting the Secrets: A Cooperative Trust Model for System-on-Chip Designs with Untrusted IPs2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI61997.2024.00066(325-330)Online publication date: 1-Jul-2024
https://doi.org/10.1109/ISVLSI61997.2024.00066
Pilato CCollini LCassano LSciuto DGarg SKarri R(2023)Optimizing the Use of Behavioral Locking for High-Level SynthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.317965142:2(462-472)Online publication date: Feb-2023
https://doi.org/10.1109/TCAD.2022.3179651
Supon TRashidzadeh R(2023)Hardware Trojan prevention using memristor technologyMicroprocessors & Microsystems10.1016/j.micpro.2023.104915102:COnline publication date: 1-Oct-2023
https://dl.acm.org/doi/10.1016/j.micpro.2023.104915
Gandhi JShekhawat DSantosh MPandey J(2023)Logic locking for IP securityComputers and Security10.1016/j.cose.2023.103196129:COnline publication date: 1-Jun-2023
https://dl.acm.org/doi/10.1016/j.cose.2023.103196
Roy AKokila JRamasubramanian NBegum B(2023)Device-specific security challenges and solution in IoT edge computing: a reviewThe Journal of Supercomputing10.1007/s11227-023-05450-679:18(20790-20825)Online publication date: 17-Jun-2023
https://doi.org/10.1007/s11227-023-05450-6
Zhong YJain ARahman MAsadizanjani NXie JGuin U(2022)AFIA: ATPG-Guided Fault Injection Attack on Secure Logic LockingJournal of Electronic Testing10.1007/s10836-022-06028-538:5(527-546)Online publication date: 3-Nov-2022
https://doi.org/10.1007/s10836-022-06028-5
Alasad QLin JYuan JFan DAwad A(2021)Resilient and Secure Hardware Devices Using ASLACM Journal on Emerging Technologies in Computing Systems10.1145/342998217:2(1-26)Online publication date: 6-Jan-2021
https://dl.acm.org/doi/10.1145/3429982
Zuzak MLiu YSrivastava A(2021)Trace Logic Locking: Improving the Parametric Space of Logic LockingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.302513540:8(1531-1544)Online publication date: Aug-2021
https://doi.org/10.1109/TCAD.2020.3025135
Chakraborty ALiu YSrivastava A(2021)Evaluating the Security of Delay-Locked CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.300884340:4(608-619)Online publication date: Apr-2021
https://doi.org/10.1109/TCAD.2020.3008843
Zuzak MSrivastava A(2020)ObfusGEM: Enhancing Processor Design Obfuscation Through Security-Aware On-Chip Memory and Data Path DesignProceedings of the International Symposium on Memory Systems10.1145/3422575.3422798(260-271)Online publication date: 28-Sep-2020
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