research-article

A modular digital VLSI flow for high-productivity SoC design

Authors:

Brucek Khailany,

Rangharajan Venkatesan,

Matthew Fojtik,

Alicia Klinefelter,

Michael Pellauer,

Nathaniel Pinckney,

Yakun Sophia Shao,

Shreesha Srinath,

Christopher Torng,

Sam (Likun) Xi,

Brian ZimmerAuthors Info & Claims

DAC '18: Proceedings of the 55th Annual Design Automation Conference

Article No.: 72, Pages 1 - 6

https://doi.org/10.1145/3195970.3199846

Published: 24 June 2018 Publication History

Abstract

A high-productivity digital VLSI flow for designing complex SoCs is presented. The flow includes high-level synthesis tools, an object-oriented library of synthesizable SystemC and C++ components, and a modular VLSI physical design approach based on fine-grained globally asynchronous locally synchronous (GALS) clocking. The flow was demonstrated on a 16nm FinFET testchip targeting machine learning and computer vision.

References

[1]

AMBA ARM. 2010. Axi protocol specification (rev 2.0). (2010).

[2]

K. Asanovic, R. Avizienis, J. Bachrach, S. Beamer, D. Biancolin, C. Celio, H. Cook, D. Dabbelt, J. Hauser, A. Izraelevitz, S. Karandikar, B. Keller, D. Kim, and J. Koenig. 2016. The Rocket Chip Generator. Technical Report UCB/EECS-2016-17. University of California at Berkeley.

[3]

J. Bachrach, H. Vo, B. Richards, Y. Lee, A. Waterman, R. Avizienis, J. Wawrzynek, and K. Asanovic. 2012. Chisel: Constructing Hardware in a Scala Embedded Language. In DAC'12. 1212--1221.

Digital Library

[4]

L.P. Carloni, K.L. McMillan, A. Saldanha, and A.L. Sangiovanni-Vincentelli. 1999. A methodology for correct-by-construction latency insensitive design. In DAC'99. 309--315.

Digital Library

[5]

Y.-H. Chen, T. Krishna, J. Emer, and V. Sze. 2016. Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks. In Proceedings of the International Solid State Circuits Conference. 262--263.

[6]

K.E. Fleming, M. Adler, M. Pellauer, A. Parashar, Arvind, and J.S. Emer. 2012. Leveraging latency-insensitivity to ease multiple FPGA design. In Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays (FPGA). 175--184.

Digital Library

[7]

D.A. Kamakshi, M. Fojtik, B. Khailany, S. Kudva, Y. Zhou, and B. Calhoun. 2016. Modeling and Analysis of Power Supply Noise Tolerance with Fine-grained GALS Adaptive Clocks. In IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC).

[8]

B. Keller, M. Fojtik, and B. Khailany. 2015. A Pausible Bisynchronous FIFO for GALS Systems. In IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 1--8.

[9]

D. Lockhart, G. Zibrat, and C. Batten. 2014. PyMTL: A Unified Framework for Vertically Integrated Computer Architecture Research. In Proceedings of the International Symposium on Microarchitecture (MICRO). 280--292.

Digital Library

[10]

M.C. McFarland, A.C. Parker, and R. Camposano. 1990. The high-level synthesis of digital systems. Proc. IEEE 78, 2 (1990), 301--318.

[11]

R.S. Nikhil and K.R. Czeck. 2010. BSV by Example: The Next-generation Language for Electronic System Design. Bluespec.

[12]

L. Piccolboni, P. Mantovani, G. Guglielmo, and L.P. Carloni. 2017. COSMOS: Coordination of High-Level Synthesis and Memory Optimization for Hardware Accelerators. ACM TECS 16, 5s (2017), 150.

Digital Library

[13]

O. Shacham, M. Wachs, A. Danowitz, S. Galal, J. Brunhaver, W. Qadeer, S. Sankaranarayanan, A. Vassiliev, S. Richardson, and M. Horowitz. 2012. Avoiding game over: Bringing design to the next level. In DAC'12. 623--629.

Digital Library

[14]

SystemC Synthesis Working Group. 2016. SystemC Synthesis Subset Standard v1.4.7. Technical Report. Accellera.

[15]

R. Zhao, G. Liu, S. Srinath, C. Batten, and Z. Zhang. 2016. Improving high-level synthesis with decoupled data structure optimization. In DAC'16. 137--142.

Digital Library

Cited By

Hasler JAyyappan PIge AMathews P(2024)A 130nm CMOS Programmable Analog Standard Cell LibraryIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2024.335507071:6(2497-2510)Online publication date: Jun-2024
https://doi.org/10.1109/TCSI.2024.3355070
Ige AYang LYang HHasler JHao C(2023)Analog System High-Level Synthesis for Energy-Efficient Reconfigurable ComputingJournal of Low Power Electronics and Applications10.3390/jlpea1304005813:4(58)Online publication date: 26-Oct-2023
https://doi.org/10.3390/jlpea13040058
Tambe TYang EKo GChai YHooper CDonato MWhatmough PRush ABrooks DWei G(2023)A 16-nm SoC for Noise-Robust Speech and NLP Edge AI Inference With Bayesian Sound Source Separation and Attention-Based DNNsIEEE Journal of Solid-State Circuits10.1109/JSSC.2022.317930358:2(569-581)Online publication date: Feb-2023
https://doi.org/10.1109/JSSC.2022.3179303
Show More Cited By

Recommendations

INVITED: A Modular Digital VLSI Flow for High-Productivity SoC Design
2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)
A high-productivity digital VLSI flow for designing complex SoCs is presented. The flow includes high-level synthesis tools, an object-oriented library of synthesizable SystemC and C++ components, and a modular VLSI physical design approach based on fine-...
An efficient and high-speed VLSI implementation of optimal normal basis multiplication over GF(2m)

Finite field multiplication is one of the most important operations in the finite field arithmetic and the main and determining building block in terms of overall speed and area in public key cryptosystems. In this work, an efficient and high-speed VLSI ...
High-Level Synthesis Design Flow for HEVC Intra Encoder on SoC-FPGA
DSD '15: Proceedings of the 2015 Euromicro Conference on Digital System Design

This paper presents a High-Level Synthesis (HLS) flow for mapping a software HEVC encoder into Altera CycloneV SoC-FPGA. The starting point is a C implementation of an open-source Kvazaar HEVC intra encoder, which is minimally refined for SystemC design ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '18: Proceedings of the 55th Annual Design Automation Conference

June 2018

1089 pages

ISBN:9781450357005

DOI:10.1145/3195970

Copyright © 2018 ACM.

© 2018 Association for Computing Machinery. ACM acknowledges that this contribution was authored or co-authored by an employee, contractor or affiliate of the United States government. As such, the United States Government retains a nonexclusive, royalty-free right to publish or reproduce this article, or to allow others to do so, for Government purposes only.

Sponsors

EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE Council on Electronic Design Automation (CEDA)

In-Cooperation

SIGBED: ACM Special Interest Group on Embedded Systems

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 24 June 2018

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

DAC '18

Sponsor:

EDAC
SIGDA

DAC '18: The 55th Annual Design Automation Conference 2018

June 24 - 29, 2018

California, San Francisco

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

13
Total Citations
View Citations
650
Total Downloads

Downloads (Last 12 months)69
Downloads (Last 6 weeks)10

Reflects downloads up to 02 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

Hasler JAyyappan PIge AMathews P(2024)A 130nm CMOS Programmable Analog Standard Cell LibraryIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2024.335507071:6(2497-2510)Online publication date: Jun-2024
https://doi.org/10.1109/TCSI.2024.3355070
Ige AYang LYang HHasler JHao C(2023)Analog System High-Level Synthesis for Energy-Efficient Reconfigurable ComputingJournal of Low Power Electronics and Applications10.3390/jlpea1304005813:4(58)Online publication date: 26-Oct-2023
https://doi.org/10.3390/jlpea13040058
Tambe TYang EKo GChai YHooper CDonato MWhatmough PRush ABrooks DWei G(2023)A 16-nm SoC for Noise-Robust Speech and NLP Edge AI Inference With Bayesian Sound Source Separation and Attention-Based DNNsIEEE Journal of Solid-State Circuits10.1109/JSSC.2022.317930358:2(569-581)Online publication date: Feb-2023
https://doi.org/10.1109/JSSC.2022.3179303
Nema SChunduru SKodigal CVoskuilen GRodrigues AHemmert SFeinberg BLee HAwad AHughes C(2023)ERAS: A Flexible and Scalable Framework for Seamless Integration of RTL Models with Structural Simulation Toolkit2023 IEEE International Symposium on Workload Characterization (IISWC)10.1109/IISWC59245.2023.00038(196-200)Online publication date: 1-Oct-2023
https://doi.org/10.1109/IISWC59245.2023.00038
Lee SWhatmough PDonato MKo GBrooks DWei G(2022)SMIV: A 16-nm 25-mm² SoC for IoT With Arm Cortex-A53, eFPGA, and Coherent AcceleratorsIEEE Journal of Solid-State Circuits10.1109/JSSC.2021.311546657:2(639-650)Online publication date: Feb-2022
https://doi.org/10.1109/JSSC.2021.3115466
Tambe THooper CPentecost LJia TYang EDonato MSanh VWhatmough PRush ABrooks DWei G(2021)EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware Multi-Task NLP InferenceMICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3466752.3480095(830-844)Online publication date: 18-Oct-2021
https://dl.acm.org/doi/10.1145/3466752.3480095
Kung HNatesh VSabot Ade Supinski BHall MGamblin T(2021)CAKEProceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis10.1145/3458817.3476166(1-14)Online publication date: 14-Nov-2021
https://dl.acm.org/doi/10.1145/3458817.3476166
Giri DChiu KEichler GMantovani PCarloni L(2021)Accelerator Integration for Open-Source SoC DesignIEEE Micro10.1109/MM.2021.307389341:4(8-14)Online publication date: 1-Jul-2021
https://doi.org/10.1109/MM.2021.3073893
Huang QKang MDinh GNorell TKalaiah ADemmel JWawrzynek JShao YMartínez JDuato JJohn L(2021)CoSAProceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00050(554-566)Online publication date: 14-Jun-2021
https://dl.acm.org/doi/10.1109/ISCA52012.2021.00050
Klinefelter A(2020)How Software Can "Chip In" to the IC Design Process: A Multidisciplinary Approach May Attract New Talent and Accelerate InnovationIEEE Solid-State Circuits Magazine10.1109/MSSC.2020.302184012:4(48-55)Online publication date: Nov-2021
https://doi.org/10.1109/MSSC.2020.3021840
Show More Cited By

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents