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INVITED: A Modular Digital VLSI Flow for High-Productivity SoC Design

Published: 24 June 2018 Publication History

Abstract

A high-productivity digital VLSI flow for designing complex SoCs is presented. The flow includes high-level synthesis tools, an object-oriented library of synthesizable SystemC and C++ components, and a modular VLSI physical design approach based on fine-grained globally asynchronous locally synchronous (GALS) clocking. The flow was demonstrated on a 16nm FinFET testchip targeting machine learning and computer vision.

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  • (2022)A Scalable Methodology for Agile Chip Development with Open-Source Hardware ComponentsProceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design10.1145/3508352.3561102(1-9)Online publication date: 30-Oct-2022

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        cover image Guide Proceedings
        2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)
        Jun 2018
        1076 pages

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        IEEE Press

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        Published: 24 June 2018

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        • (2022)A Scalable Methodology for Agile Chip Development with Open-Source Hardware ComponentsProceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design10.1145/3508352.3561102(1-9)Online publication date: 30-Oct-2022

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