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Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms

Authors:

Kevin K. Chang,

Abdullah Giray Yağlıkçı,

Saugata Ghose,

Aditya Agrawal,

Niladrish Chatterjee,

Onur MutluAuthors Info & Claims

ACM SIGMETRICS Performance Evaluation Review, Volume 45, Issue 1

Page 52

https://doi.org/10.1145/3143314.3078590

Published: 05 June 2017 Publication History

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Abstract

The energy consumption of DRAM is a critical concern in modern computing systems. Improvements in manufacturing process technology have allowed DRAM vendors to lower the DRAM supply voltage conservatively, which reduces some of the DRAM energy consumption. We would like to reduce the DRAM supply voltage more aggressively, to further reduce energy. Aggressive supply voltage reduction requires a thorough understanding of the effect voltage scaling has on DRAM access latency and DRAM reliability. In this paper, we take a comprehensive approach to understanding and exploiting the latency and reliability characteristics of modern DRAM when the supply voltage is lowered below the nominal voltage level specified by manufacturers.

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Yağlıkçı ATuğrul YOliveira GYüksel İOlgun ALuo HMutlu O(2024)Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA57654.2024.00048(560-577)Online publication date: 2-Mar-2024
https://doi.org/10.1109/HPCA57654.2024.00048
Yüksel İTuğrul YOlgun ABostancı FYağlıkçı AOliveira GLuo HGómez-Luna JSadrosadati MMutlu O(2024)Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA57654.2024.00030(280-296)Online publication date: 2-Mar-2024
https://doi.org/10.1109/HPCA57654.2024.00030
Yüksel İTuğrul YBostancı FOliveira GYağlıkçı AOlgun ASoysal MLuo HGómez-Luna JSadrosadati MMutlu O(2024)Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis2024 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)10.1109/DSN58291.2024.00024(99-114)Online publication date: 24-Jun-2024
https://doi.org/10.1109/DSN58291.2024.00024
Show More Cited By

Index Terms

Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms
1. Computer systems organization
  1. Dependable and fault-tolerant systems and networks
    1. Processors and memory architectures
2. Hardware

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Information & Contributors

Information

Published In

ACM SIGMETRICS Performance Evaluation Review Volume 45, Issue 1

Performance evaluation review

June 2017

70 pages

ISSN:0163-5999

DOI:10.1145/3143314

Editor:
Nidhi Hegde
Bell Labs, Nokia

Issue’s Table of Contents

SIGMETRICS '17 Abstracts: Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems
June 2017
84 pages
ISBN:9781450350327
DOI:10.1145/3078505
General Chairs:
Bruce Hajek
University of Illinois
,
Sewoong Oh
University of Illinois
,
Program Chairs:
Augustin Chaintreau
Columbia University
,
Leana Golubchik
University of Southern California
,
Zhi-Li Zhang
University of Minnesota

Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 June 2017

Published in SIGMETRICS Volume 45, Issue 1

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Nvidia
Samsung
Semiconductor Research Corporation
Google
National Science Foundation
Intel Corporation

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Yağlıkçı ATuğrul YOliveira GYüksel İOlgun ALuo HMutlu O(2024)Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA57654.2024.00048(560-577)Online publication date: 2-Mar-2024
https://doi.org/10.1109/HPCA57654.2024.00048
Yüksel İTuğrul YOlgun ABostancı FYağlıkçı AOliveira GLuo HGómez-Luna JSadrosadati MMutlu O(2024)Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA57654.2024.00030(280-296)Online publication date: 2-Mar-2024
https://doi.org/10.1109/HPCA57654.2024.00030
Yüksel İTuğrul YBostancı FOliveira GYağlıkçı AOlgun ASoysal MLuo HGómez-Luna JSadrosadati MMutlu O(2024)Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis2024 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)10.1109/DSN58291.2024.00024(99-114)Online publication date: 24-Jun-2024
https://doi.org/10.1109/DSN58291.2024.00024
Orosa LRührmair UGiray Yağlikçi ALuo HOlgun AJattke PPatel MKim JRazavi KMutlu O(2024)SpyHammer: Understanding and Exploiting RowHammer Under Fine-Grained Temperature VariationsIEEE Access10.1109/ACCESS.2024.340938912(80986-81003)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3409389
Nguyen NAhmed AAbdallah ADang K(2023)Power-Aware Neuromorphic Architecture With Partial Voltage Scaling 3-D Stacking Synaptic MemoryIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.331823131:12(2016-2029)Online publication date: 1-Dec-2023
https://dl.acm.org/doi/10.1109/TVLSI.2023.3318231
Olgun AHassan HYağlıkçı ATuğrul YOrosa LLuo HPatel MErgin OMutlu O(2023)DRAM Bender: An Extensible and Versatile FPGA-Based Infrastructure to Easily Test State-of-the-Art DRAM ChipsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.328217242:12(5098-5112)Online publication date: Dec-2023
https://doi.org/10.1109/TCAD.2023.3282172
Yahya JVolos HBartolini DAntoniou GKim JWang ZKalaitzidis KRollet TChen ZGeng YMutlu OSazeides Y(2022)AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server Applications2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO56248.2022.00063(835-850)Online publication date: Oct-2022
https://doi.org/10.1109/MICRO56248.2022.00063
Yaglikci AOlgun APatel MLuo HHassan HOrosa LErgin OMutlu O(2022)HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO56248.2022.00062(815-834)Online publication date: Oct-2022
https://doi.org/10.1109/MICRO56248.2022.00062
Bostanci FOlgun AOrosa LYaglikci AKim JHassan HErgin OMutlu O(2022)DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA53966.2022.00087(1141-1155)Online publication date: Apr-2022
https://doi.org/10.1109/HPCA53966.2022.00087
Yaglikci ALuo HDe Oliviera GOlgun APatel MPark JHassan HKim JOrosa LMutlu O(2022)Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices2022 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)10.1109/DSN53405.2022.00054(475-487)Online publication date: Jun-2022
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