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Effective iterative techniques for fingerprinting design IP

Published: 01 June 1999 Publication History
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References

[1]
C.J. Alpert, "Partitioning Benchmarks for the VLSI CAD Community", http://vls icad. cs. ucla. edu/~ chee se/benchmarks, html
[2]
C.J. Alpert, "The ISPD-98 Circuit Benchmark Suite", P~vc. ACM/IEEE International Symposium on Physical Design, April 98, pp. 80-85. See errata at http://vls icad. cs. ucla. edu/~ chee se/errata, html
[3]
I. Biehl and B. Meyer, "Protocols for Collusion-Secure Asymmetric Fingerprinting'', Plvc. 14th Annual Symposium on Theoretical Aspect of Computer Science, Springer-Verlag, 1997, pp. 399-412.
[4]
D. Boneh and J. Shaw, "Collusion-Secure Fingerprinting for Digital Data", P~vc. 15th annual International Cryptology Conference, Springer-Verlag, 1995, pp. 452-465.
[5]
S. Dutt and W. Deng, "VLSI Circuit Partitioning by Cluster-Removal Using Iterative Improvement Techniques", P~vc. IEEE International Conference on Computer-Aided Design, 1996, pp. 194-200.
[6]
C.M. Fiduccia and R. M. Mattheyses, "A Linear Time Heuristic for Improving Network Partitions", P~vc. ACM/IEEE Design Automation Conference, 1982, pp. 175-181.
[7]
M.R. Garey and D. S. Johnson, Computers and Intractability: A Guide to the Theory of NP-completeness, New York, W. H. Freeman and Company, 1979.
[8]
I. Hong and M. Potkonjak, "Behavioral Synthesis Techniques for Intellectual Property Protection", unpublished manuscript, 1997.
[9]
A. B. Kahng, J. Lach, W. H. Mangione-Smith, S. Mantik, I. L. Markov, M. Potkonjak, P. Tucker, H. Wang and G. WoMb, "Watermarking Techniques for Intellectual Property Protection", P~vc. ACM/IEEE Design Automation Conference, June 1998, pp. 776-781.
[10]
A.B. Kahng, S. Mantik, I. L. Markov, M. Potkonjak, P. Tucker, H. Wang and G. WoMb, "Robust IP Watermarking Methodologies for Physical Design", P~vc. ACM/IEEE Design Automation Conference, June 1998, pp. 782-787.
[11]
B.W. Kemighan and S. Lin, "An Efficient Heuristic Procedure for Partitioning Graphs", Bell System Tech. Journal 49 (1970), pp. 291-307.
[12]
D. Kirovski, Y. Hwang, M. Potkonjak and J. Cong, "Intellectual Property Protection by Watermarking Combinational Logic Synthesis Solutions", P~vc. IEEE/ACM International Conference on Computer Aided Design, 1998.
[13]
J.Lach, W.H.Mangione-Smith and M.Potkonjak, "FPGA Fingerprinting Techniques for Protecting Intellectual Property", P~vceedings of CICC, 1998.
[14]
I. H. Osman and J. P. Kelly, eds., Meta-Heuristics: Theory and Applications, Kluwer, 1996.
[15]
B. Pfitzmann, and M. Schunter, "Asymmetic Fingerprinting", P~vc. International Conference on the Theory and Application of Cryptographic Techniques, Springer-Verlag, 1996, pp. 84-95.
[16]
G. Qu and M. Potkonjak, "Analysis of Watermarking Techniques for Graph Coloring Problem", Proc. IEEE/ACM International Conference on Computer Aided Design, 1998.
[17]
R. H. Storer, S. D. Wu and R. Vaccari, "New Search Spaces for Sequencing Problems With Application to Job Shop Scheduling", Management Science 38 (1992), pp. 1495-1509.
[18]
http://dimacs.rutgers.edu/
[19]
http://aida'intellektik'inIbrmatik'th-darmstadt'deFh~~s/SATLIB/

Cited By

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  • (2023)Making a Case for Logic LockingUnderstanding Logic Locking10.1007/978-3-031-37989-5_4(63-87)Online publication date: 26-Jun-2023
  • (2021)Integrated Circuit Digital Fingerprinting–Based AuthenticationAuthentication of Embedded Devices10.1007/978-3-030-60769-2_1(3-27)Online publication date: 23-Jan-2021
  • (2019)The Need for Logic LockingTrustworthy Hardware Design: Combinational Logic Locking Techniques10.1007/978-3-030-15334-2_1(1-16)Online publication date: 5-Sep-2019
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      cover image ACM Conferences
      DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation Conference
      June 1999
      1000 pages
      ISBN:1581131097
      DOI:10.1145/309847
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Published: 01 June 1999

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      Cited By

      View all
      • (2023)Making a Case for Logic LockingUnderstanding Logic Locking10.1007/978-3-031-37989-5_4(63-87)Online publication date: 26-Jun-2023
      • (2021)Integrated Circuit Digital Fingerprinting–Based AuthenticationAuthentication of Embedded Devices10.1007/978-3-030-60769-2_1(3-27)Online publication date: 23-Jan-2021
      • (2019)The Need for Logic LockingTrustworthy Hardware Design: Combinational Logic Locking Techniques10.1007/978-3-030-15334-2_1(1-16)Online publication date: 5-Sep-2019
      • (2019)Privacy and Audiovisual Content: Protecting Users as Big Multimedia Data Grows BiggerBig Data Analytics for Large‐Scale Multimedia Search10.1002/9781119376996.ch7(183-208)Online publication date: 15-Mar-2019
      • (2018)Hardware Security and Trust: Logic Locking as a Design-for-Trust SolutionThe IoT Physical Layer10.1007/978-3-319-93100-5_20(353-373)Online publication date: 4-Sep-2018
      • (2016)Hardware IP Watermarking and FingerprintingSecure System Design and Trustable Computing10.1007/978-3-319-14971-4_10(329-368)Online publication date: 2016
      • (2016)Digital Fingerprint: A Practical Hardware Security PrimitiveDigital Fingerprinting10.1007/978-1-4939-6601-1_6(89-114)Online publication date: 26-Oct-2016
      • (2015)A practical circuit fingerprinting method utilizing observability don't care conditionsProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744780(1-6)Online publication date: 7-Jun-2015
      • (2013)Circuit partitioning based fingerprinting method for IP protectionIEICE Electronics Express10.1587/elex.10.2013013810:7(20130138-20130138)Online publication date: 2013
      • (2010)Digital Rights ManagementThe Practical Handbook of Internet Computing10.1201/9780203507223.ch21Online publication date: 31-Jan-2010
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