research-article

LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations

Authors:

Michihiro Shintani,

Masayuki Hiromoto,

Takashi SatoAuthors Info & Claims

DAC '17: Proceedings of the 54th Annual Design Automation Conference 2017

Article No.: 66, Pages 1 - 6

https://doi.org/10.1145/3061639.3062280

Published: 18 June 2017 Publication History

Abstract

As the transistor process technology continues to scale, the aging effect posits new challenges to the already complex static timing analysis (STA) process. In this paper, we first observe that aging can be thought of a type of correlated dynamic on-chip variations (OCV), and identify the problem introduced by such type of OCV. In particular, we take the negative bias temperature instability (NBTI) as an example dynamic OCV mechanism. We then propose a learning-based STA (LSTA) library to "predict" the timing of gates by capturing the correlation between our designed predictors. In the experiment, we used a linear regressor, support vector regression, and a non-linear method, random forest, to create the prediction model. An ISCAS'89 benchmark circuit is used as a training sample to for the algorithms to learn the aging model of gates, and the accuracies of the model is then tested on two processor-scale designs using the library are evaluated, achieving a maximum absolute error of 3.42%.

References

[1]

OpenCores. http://www.opencores.org.

[2]

M. A. Alam and S. Mahapatra. A comprehensive model of PMOS NBTI degradation. Microelectron. Reliab., 45(1):71--81, 2005.

[3]

S. Bhardwaj, W. Wang, R. Vattikonda, Y. Cao, and S. Vrudhula. Predictive modeling of the NBTI effect for reliable design. In Proc. CICC, pages 189--192, 2006.

[4]

S. Bian, M. Shintani, S. Morita, M. Hiromoto, and T. Sato. Nonlinear delay-table approach for full-chip NBTI degradation prediction. In Proc. ISQED, pages 307--312, 2016.

[5]

L. Breiman. Bagging predictors. Machine learning, 24(2):123--140, 1996.

[6]

F. Brglez, D. Bryan, and K. Koiminski. Combinational profiles of sequential benchmark circuits. In Proc. ISCAS, pages 1929--1934, 1989.

[7]

W. T. J. Chan, K. Y. Chung, A. B. Kahng, et al. Learning-based prediction of embedded memory timing failures during initial floorplan design. In Proc. ASPDAC, pages 178--185, 2016.

Digital Library

[8]

P. Chaparala, J. Shibley, and P. Lim. Threshold voltage drift in PMOSFETs due to NBTI and HCI. In Proc. IIRW, pages 95--97, 2000.

[9]

F. Firouzi, S. Kiamehr, M. Tahoori, and S. Nassif. Incorporating the impacts of workload-dependent runtime variations into timing analysis. In Proc. DATE, pages 1022--1025, 2013.

Digital Library

[10]

S.-S. Han, A. B. Kahng, S. Nath, and A. S. Vydyanathan. A deep learning methodology to proliferate golden signoff timing. In Proc. DATE, pages 1--6, 2014.

Digital Library

[11]

A. B. Kahng, M. Luo, and S. Nath. SI for free: machine learning of interconnect coupling delay and transition effects. In Proc. SLIP, pages 1--8, 2015.

[12]

S. Karapetyan and U. Schlichtmann. Integrating aging aware timing analysis into a commercial STA tool. In Proc. VLSI-DAT, pages 1--4, 2015.

[13]

H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye. Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration. In Proc. ISQED, pages 646--651, 2010.

[14]

S. Mahapatra, P. Bharath Kumar, and M. Alam. A new observation of enhanced bias temperature instability in thin gate oxide p-MOSFETs. In IEDM Tech. Digest, pages 337--340, 2003.

[15]

M. Pal and P. M. Mather. An assessment of the effectiveness of decision tree methods for land cover classification. Remote sensing of environment, 86(4):554--565, 2003.

[16]

R. E. Schapire, Y. Freund, P. Bartlett, and W. S. Lee. Boosting the margin: A new explanation for the effectiveness of voting methods. Annals of statistics, pages 1651--1686, 1998.

[17]

Si2.org. Nangate 45nm open cell library. http://www.si2.org.

[18]

Synopsys, Inc. Design Compiler I-2013.06.

[19]

Synopsys, Inc. HSPICE I-2013.12.

[20]

Synopsys, Inc. PrimeTime Fundamental H-2013.06.

[21]

Synopsys, Inc. Processor Designer G-2012.09.

[22]

University of California, Berkeley. Bsim4v4.7, University of California, 2011. http://www-device.eecs.berkeley.edu/bsim/Files/BSIM4/BSIM470.

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Jiang WZhao ZLuo ZZhou JZhang SHu BBian P(2024)TSTL-GNN: Graph-Based Two-Stage Transfer Learning for Timing Engineering Change Order Analysis AccelerationElectronics10.3390/electronics1315289713:15(2897)Online publication date: 23-Jul-2024
https://doi.org/10.3390/electronics13152897
Tan XDomanski PBanerjee SChakrabarty KAmrouch HHu JGarg SLin Y(2024)ML-TIME: ML-driven Timing Analysis of Integrated Circuits in the Presence of Process Variations and Aging EffectsProceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD10.1145/3670474.3685968(1-9)Online publication date: 9-Sep-2024
https://dl.acm.org/doi/10.1145/3670474.3685968
Kai-Chun Chang KLiu GChiang CLee PHui-Ru Jiang I(2024)Multi-Corner Timing Macro Modeling With Neural Collaborative Filtering From Recommendation Systems PerspectiveIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.338335043:10(2840-2853)Online publication date: Oct-2024
https://doi.org/10.1109/TCAD.2024.3383350
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cover image ACM Conferences

DAC '17: Proceedings of the 54th Annual Design Automation Conference 2017

June 2017

533 pages

ISBN:9781450349277

DOI:10.1145/3061639

Copyright © 2017 ACM.

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Published: 18 June 2017

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Japan Society for the Promotion of Science

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DAC '17

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DAC '17: The 54th Annual Design Automation Conference 2017

June 18 - 22, 2017

TX, Austin, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Jiang WZhao ZLuo ZZhou JZhang SHu BBian P(2024)TSTL-GNN: Graph-Based Two-Stage Transfer Learning for Timing Engineering Change Order Analysis AccelerationElectronics10.3390/electronics1315289713:15(2897)Online publication date: 23-Jul-2024
https://doi.org/10.3390/electronics13152897
Tan XDomanski PBanerjee SChakrabarty KAmrouch HHu JGarg SLin Y(2024)ML-TIME: ML-driven Timing Analysis of Integrated Circuits in the Presence of Process Variations and Aging EffectsProceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD10.1145/3670474.3685968(1-9)Online publication date: 9-Sep-2024
https://dl.acm.org/doi/10.1145/3670474.3685968
Kai-Chun Chang KLiu GChiang CLee PHui-Ru Jiang I(2024)Multi-Corner Timing Macro Modeling With Neural Collaborative Filtering From Recommendation Systems PerspectiveIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.338335043:10(2840-2853)Online publication date: Oct-2024
https://doi.org/10.1109/TCAD.2024.3383350
Chong AHoe SKeong K(2024)Delay Aware Reduced SPEF STA2024 IEEE Symposium on Industrial Electronics & Applications (ISIEA)10.1109/ISIEA61920.2024.10607331(1-6)Online publication date: 6-Jul-2024
https://doi.org/10.1109/ISIEA61920.2024.10607331
Tu KTang XYu CJosipović LChu ZTu KTang XYu CJosipović LChu Z(2024)Performance (Timing) AnalysisFPGA EDA10.1007/978-981-99-7755-0_5(73-78)Online publication date: 1-Feb-2024
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Amuru DZahra AVudumula HCherupally PGurram SAhmad AAbbas Z(2023)AI/ML algorithms and applications in VLSI design and technologyIntegration10.1016/j.vlsi.2023.06.00293(102048)Online publication date: Nov-2023
https://doi.org/10.1016/j.vlsi.2023.06.002
Zhao ZZhang SLiu GFeng CYang THan AWang L(2022)Machine-Learning-Based Multi-Corner Timing Prediction for Faster Timing ClosureElectronics10.3390/electronics1110157111:10(1571)Online publication date: 13-May-2022
https://doi.org/10.3390/electronics11101571
Gubbi KBeheshti-Shirazi SSheaves TSalehi SPD SRafatirad SSasan AHomayoun HSavidis ISasan AThapliyal HDeMara R(2022)Survey of Machine Learning for Electronic Design AutomationProceedings of the Great Lakes Symposium on VLSI 202210.1145/3526241.3530834(513-518)Online publication date: 6-Jun-2022
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Varghese MMuthumanickam T(2022)Machine Learning Approaches for Electronic Design Automation in IC Design Flow2022 Sixth International Conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC)10.1109/I-SMAC55078.2022.9987302(528-533)Online publication date: 10-Nov-2022
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