Abstract
Timing analysis can be static or dynamic. Dynamic timing analysis (DTA) verifies functionality of the design by applying input vectors and checking for correct output vectors whereas static timing analysis (STA) checks static delay requirements of the circuit without any input or output vectors. In this chapter, STA techniques is focused since it is widely used in FPGA design flow to make sure the timing requirements are met.
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References
IEEE standard for standard delay format (SDF) for the electronic design process, in IEEE Std. 1497-2001 (2001), pp. 1–80
J.L.M. Lee, A scalable method to measure similarity between two EDA-generated timing graphs, in 2015 International Conference on Computer, Communications, and Control Technology (I4CT) (2015), pp. 44–48
Intel, Guaranteeing silicon performance with FPGA timing models. https://cdrdv2-public.intel.com/650314/wp-01139-timing-model.pdf
T.-W. Huang, M.D.F. Wong, UI-timer 1.0: an ultrafast path-based timing analysis algorithm for CPPR. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 35(11), pp. 1862–1875 (2016)
D. Mishagli, E. Koskin, E. Blokhina, Path-based statistical static timing analysis for large integrated circuits in a weak correlation approximation, in 2019 IEEE International Symposium on Circuits and Systems (ISCAS) (2019), pp. 1–5
L.-W. Chen, Y.-N. Sui, T.-C. Lee, Y.-L. Li, M.C.-T. Chao, I.-C. Tsai, T.-W. Kung, E.-C. Liu, Y.-C. Chang, Path-based pre-routing timing prediction for modern very large-scale integration designs, in 2022 23rd International Symposium on Quality Electronic Design (ISQED) (2022), pp. 1–6
J. Lu, N. Xu, J. Yu, T. Weng, Research of timing graph traversal algorithm in static timing analysis based on FPGA, in 2017 IEEE 3rd Information Technology and Mechatronics Engineering Conference (ITOEC) (2017), pp. 334–338
L. Zhang, Y. Hu, C.-P. Chen, Block based statistical timing analysis with extended canonical timing model, in Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005., vol. 1 (2005), pp. 250–253
R. Chen, H. Zhou, New block-based statistical timing analysis approaches without moment matching, in Proceedings of the ASP-DAC 2007—Asia and South Pacific Design Automation Conference 2007, Series. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (2007), pp. 462–467
G. Luo, B. Jin, W. Zhang, A fast and simple block-based approach for common path pessimism removal in static timing analysis, in 2015 14th International Conference on Computer-Aided Design and Computer Graphics (CAD/Graphics) (2015), pp. 234–235
L. Jin, W. Fu, Y. Zheng, H. Yan, A precise block-based statistical timing analysis with max approximation using multivariate adaptive regression splines, in 2019 IEEE 13th International Conference on ASIC (ASICON) (2019), pp. 1–4
T.-W. Huang, M.D.F. Wong, OpenTimer: a high-performance timing analysis tool, in 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (2015), pp. 895–902
J. Bhasker, R. Chadha, Static Timing Analysis for Nanometer Designs: A Practical Approach, 1st edn. (Springer, 2009)
Y.-M. Yang, Y.-W. Chang, I.H.-R. Jiang, iTimerC: common path pessimism removal using effective reduction methods, in 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (2014), pp. 600–605
T.-W. Huang, M.D.F. Wong, D. Sinha, K. Kalafala, N. Venkateswaran, A distributed timing analysis framework for large designs, in Proceedings of the 53rd Annual Design Automation Conference, Series DAC ’16 (Association for Computing Machinery, New York, NY, USA, 2016). Available https://doi.org/10.1145/2897937.2897959
K. E. Murray, V. Betz, Tatum: parallel timing analysis for faster design cycles and improved optimization, in 2018 International Conference on Field-Programmable Technology (FPT) (2018), pp. 110–117
T.-W. Huang, G. Guo, C.-X. Lin, M.D.F. Wong, OpenTimer v2: a new parallel incremental timing analysis engine. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 40(4):776–789 (2021)
Z. Guo, T.-W. Huang, Y. Lin, GPU-accelerated static timing analysis, in 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD) (2020), pp. 1–9
S. Bian, M. Shintani, M. Hiromoto, T. Sato, LSTA: learning-based static timing analysis for high-dimensional correlated on-chip variations, in Proceedings of the 54th Annual Design Automation Conference 2017, Series DAC ’17 (Association for Computing Machinery, New York, NY, USA, 2017). Available https://doi.org/10.1145/3061639.3062280
A.B. Kahng, U. Mallappa, L. Saul, Using machine learning to predict path-based slack from graph-based timing analysis, in 2018 IEEE 36th International Conference on Computer Design (ICCD) (2018), pp. 603–612
M.A. Savari, H. Jahanirad, NN-SSTA: a deep neural network approach for statistical static timing analysis, Expert Syst. Appl. 149, 113309 (2020). Available https://www.sciencedirect.com/science/article/pii/S0957417420301342
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Tu, K., Tang, X., Yu, C., Josipović, L., Chu, Z. (2024). Performance (Timing) Analysis. In: FPGA EDA. Springer, Singapore. https://doi.org/10.1007/978-981-99-7755-0_5
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DOI: https://doi.org/10.1007/978-981-99-7755-0_5
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