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The edge-based design rule model revisited

Editor: C. L. Liu Authors:

Michael A. Riepe,

Karem A. SakallahAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 3, Issue 3

Pages 463 - 486

https://doi.org/10.1145/293625.293633

Published: 01 July 1998 Publication History

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Abstract

A model for integrated circuit design rules based on rectangle edge constraints has been proposed by Jeppson, Christensson, and Hedenstierna. This model appears to be the most rigorous proposed to date for the description of such edge-based design rules. However, in certain rare circumstances their model is unable to express the correct design rule when the constrained edges are not adjacent in the layout. We introduce a new notation, called an edge path, which allows us to extend their model to allow for constraints between edges separated by an arbitrary number of intervening edges. Using this notation we enumerate all edge paths that are required to correctly model the original design rule macros of the JCH model, and prove that these macros are sufficient to model the most common rules. We also show how this notation alows us to directly specify many kinds of conditional design rules that required ad hoc specification under the JCH model.

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Cited By

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Kim RHwang SOak AShirazi YChang HYang KMirabelli G(2024)Curvilinear Standard Cell Design for Semiconductor ManufacturingIEEE Transactions on Semiconductor Manufacturing10.1109/TSM.2024.336290037:2(152-159)Online publication date: May-2024
https://doi.org/10.1109/TSM.2024.3362900
He ZYu B(2023)Invited Paper: Heterogeneous Acceleration for Design Rule Checking2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323957(1-7)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323957
Said HDessouky MEl-Adawi RAbbas HShahein H(2010)Analog Layout RetargetingAnalog Layout Synthesis10.1007/978-1-4419-6932-3_5(205-242)Online publication date: 25-Aug-2010
https://doi.org/10.1007/978-1-4419-6932-3_5
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Index Terms

The edge-based design rule model revisited
1. Applied computing
  1. Physical sciences and engineering
    1. Engineering
2. Hardware
  1. Hardware validation
    1. Functional verification

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 3, Issue 3

July 1998

206 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/293625

Editor:
C. L. Liu
Univ. of Illinois at Urbana-Champaign, Urbana

Issue’s Table of Contents

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Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 July 1998

Published in TODAES Volume 3, Issue 3

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Kim RHwang SOak AShirazi YChang HYang KMirabelli G(2024)Curvilinear Standard Cell Design for Semiconductor ManufacturingIEEE Transactions on Semiconductor Manufacturing10.1109/TSM.2024.336290037:2(152-159)Online publication date: May-2024
https://doi.org/10.1109/TSM.2024.3362900
He ZYu B(2023)Invited Paper: Heterogeneous Acceleration for Design Rule Checking2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323957(1-7)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323957
Said HDessouky MEl-Adawi RAbbas HShahein H(2010)Analog Layout RetargetingAnalog Layout Synthesis10.1007/978-1-4419-6932-3_5(205-242)Online publication date: 25-Aug-2010
https://doi.org/10.1007/978-1-4419-6932-3_5
Rajagopalan SBhattacharya SBatterywala S(2009)Efficient Analog/RF Layout Closure with Compaction Based LegalizationProceedings of the 2009 22nd International Conference on VLSI Design10.1109/VLSI.Design.2009.61(137-142)Online publication date: 5-Jan-2009
https://dl.acm.org/doi/10.1109/VLSI.Design.2009.61
Fu DChaung YLin YLi Y(2009)Topology-driven cell layout migration with collinear constraints2009 IEEE International Conference on Computer Design10.1109/ICCD.2009.5413118(439-444)Online publication date: Oct-2009
https://doi.org/10.1109/ICCD.2009.5413118
Bhattacharya SBatterywala SRajagopalan SMa HShenoy N(2008)On Efficient and Robust Constraint Generation for Practical Layout Legalization9th International Symposium on Quality Electronic Design (isqed 2008)10.1109/ISQED.2008.4479761(379-384)Online publication date: Mar-2008
https://doi.org/10.1109/ISQED.2008.4479761
Zhu JFang FTang Q(2006)CalligrapherIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2005.85204024:9(1347-1361)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2005.852040
Koranne S(2004)A high performance SIMD framework for design rule checking on Sony's PlayStation 2 Emotion Engine platform [IC layout]SCS 2003. International Symposium on Signals, Circuits and Systems. Proceedings (Cat. No.03EX720)10.1109/ISQED.2004.1283702(371-376)Online publication date: 2004
https://doi.org/10.1109/ISQED.2004.1283702

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Abstract

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Recommendations

Efficient Design Rule Checking Script Generation via Key Information Extraction

Design Rule Checking with a CNN Based Feature Extractor

Design Rule Management and its Applications in 15nm FreePDK Technology

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