Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization

Pulsed latches, latches driven by a brief clock pulse, offer the same convenience of timing verification and optimization as flip-flop-based circuits, while retaining the advantages of latches over flip-flops. But a pulsed latch that uses a single pulse ...

Although it is well-known that substituting level-sensitive latches for edge-triggered registers can boost circuit performance, results of measuring the performance gained by using latches in real circuits-when retiming is used to optimize the ...

As the size and complexity of embedded systems are growing, the area cost and performance of the LSI circuits are becoming more crucial. A critical bottleneck for them is interconnections such as multiplexers (MUXs). Thus, a hardware synthesis technique ...