On Improving the Performance of Hybrid Wired-Wireless Network-on-Chip Architectures
Pages 27 - 32
Abstract
Recently, hybrid wired-wireless Network-on-Chip (WiNoC) have been proposed to meet the performance and scalability demands of modern System-on-Chip (SoC) design. However, due to the presence of wirelines with multi-hop nodes in the hybrid architecture, WiNoCs have reduced performance efficiency. In this paper, we propose a low-complexity single-cycle bypassing mechanism to alleviate the performance degradation in such emerging hybrid NoCs. The proposed router employs both dimension-ordered routing (DoR) and a deadlock free adaptive routing to transmit flits at low-loads and high traffic loads, respectively, to efficiently balance traffic in WiNoCs. By reducing the latency between the wired nodes and the wireless nodes, the proposed router can improve performance efficiency in terms of average packet delay by an average of 50% in WiNoCs.
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Published In
October 2016
56 pages
ISBN:9781450347921
DOI:10.1145/2994133
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Published: 15 October 2016
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NoCArc'16
NoCArc'16: 9th International Workshop on Network on Chip Architectures
October 15, 2016
Taipei, Taiwan
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NoCArc '16 Paper Acceptance Rate 8 of 20 submissions, 40%;
Overall Acceptance Rate 46 of 122 submissions, 38%
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