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Student Research Poster: A Low Complexity Cache Sharing Mechanism to Address System Fairness

Published: 11 September 2016 Publication History

Abstract

Shared caches have become, de facto, the common design choice in current multi-cores, ranging from embedded devices to high-performance processors. In these systems, requests from multiple applications compete for the cache resources, degrading to different extents their progress, quantified as the performance of individual applications compared to isolated execution. The difference between the progresses of the running applications yields the system to unpredictable behavior and causes a fairness problem. This problem can be addressed by carefully partitioning cache resources among the contending applications, but to be effective, a partitioning approach needs to estimate per-application progress. This work proposes Fair-Progress Cache Partitioning (FPCP), a low-overhead cache partitioning approach which addresses fairness by distributing cache resources among applications depending on their progress. To estimate progress, we have implemented two state-of-the-art performance models, ASM and PTCA, which estimate, at runtime, the performance a given application would have if executed in isolation.

References

[1]
K. Du Bois, S. Eyerman, and L. Eeckhout. Per-thread cycle accounting in multicore processors. ACM Trans. Archit. Code Optim., 9(4):29:1--29:22, 2013.
[2]
M. Qureshi and Y. Patt. Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches. In MICRO, pages 423--432, 2006.
[3]
L. Subramanian, V. Seshadri, A. Ghosh, S. Khan, and O. Mutlu. The application slowdown model: Quantifying and controlling the impact of inter-application interference at shared caches and main memory. In MICRO, pages 62--75, 2015.

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  1. Student Research Poster: A Low Complexity Cache Sharing Mechanism to Address System Fairness

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          Published In

          cover image ACM Conferences
          PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and Compilation
          September 2016
          474 pages
          ISBN:9781450341219
          DOI:10.1145/2967938
          Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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          Association for Computing Machinery

          New York, NY, United States

          Publication History

          Published: 11 September 2016

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          Author Tags

          1. cache partitioning
          2. multi-cores
          3. progress
          4. slowdown
          5. unfairness

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          • Abstract

          Funding Sources

          • MINECO, explora
          • MINECO, plan E
          • Valencian Government

          Conference

          PACT '16
          Sponsor:
          • IFIP WG 10.3
          • IEEE TCCA
          • SIGARCH
          • IEEE CS TCPP

          Acceptance Rates

          PACT '16 Paper Acceptance Rate 31 of 119 submissions, 26%;
          Overall Acceptance Rate 121 of 471 submissions, 26%

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          PACT '24

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