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- research-articleJanuary 2024
RSPP: Restricted Static Pseudo-Partitioning for Mitigation of Cross-Core Covert Channel Attacks
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 29, Issue 2Article No.: 27, Pages 1–22https://doi.org/10.1145/3637222Cache timing channel attacks exploit the inherent properties of cache memories: hit and miss time along with the shared nature of the cache to leak secret information. The side channel and covert channel are the two well-known cache timing channel ...
- research-articleNovember 2023
Modelling Data Locality of Sparse Matrix-Vector Multiplication on the A64FX
SC-W '23: Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, Network, Storage, and AnalysisPages 1334–1342https://doi.org/10.1145/3624062.3624198One of the novel features of the Fujitsu A64FX CPU is the sector cache. This feature enables hardware-supported partitioning of the L1 and L2 caches and allows the programmer control of which partition is used to place data in. This paper performs an in-...
- research-articleDecember 2023
McCore: A Holistic Management of High-Performance Heterogeneous Multicores
MICRO '23: Proceedings of the 56th Annual IEEE/ACM International Symposium on MicroarchitecturePages 1044–1058https://doi.org/10.1145/3613424.3614295Heterogeneous multicore systems have emerged as a promising approach to scale performance in high-end desktops within limited power and die size constraints. Despite their advantages, these systems face three major challenges: memory bandwidth ...
- research-articleJune 2023
Minimizing Cache Usage for Real-time Systems
RTNS '23: Proceedings of the 31st International Conference on Real-Time Networks and SystemsPages 200–211https://doi.org/10.1145/3575757.3593651Cache partitioning is a technique to reduce interference among tasks accessing the shared caches. To make this technique effective, cache segments must be given to the tasks that can benefit most from having their data and instructions cached for ...
- research-articleJune 2023
MFence: Defending Against Memory Access Interference in a Disaggregated Cloud Memory Platform
- Jinhoon Lee,
- Yeonwoo Jung,
- Suyeon Lee,
- Safdar Jamil,
- Sungyong Park,
- Kwangwon Koh,
- Hongyeon Kim,
- Youngjae Kim,
- Kangho Kim
SAC '23: Proceedings of the 38th ACM/SIGAPP Symposium on Applied ComputingPages 1309–1317https://doi.org/10.1145/3555776.3577714A VM-based disaggregated cloud memory platform (DCM) virtualizes the memory device of a remote server connected to a highspeed network as an expansion of local memory. DCM provides large memory to applications to increase throughput. However, DCM is not ...
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Com-CAS: Effective Cache Apportioning under Compiler Guidance
PACT '22: Proceedings of the International Conference on Parallel Architectures and Compilation TechniquesPages 14–27https://doi.org/10.1145/3559009.3569645With a growing number of cores in modern high-performance servers, effective sharing of the last level cache (LLC) is more critical than ever. The primary agenda of such systems is to maximize performance by efficiently supporting multi-tenancy of ...
- research-articleAugust 2022
Predictable sharing of last-level cache partitions for multi-core safety-critical systems
DAC '22: Proceedings of the 59th ACM/IEEE Design Automation ConferencePages 1273–1278https://doi.org/10.1145/3489517.3530614Last-level cache (LLC) partitioning is a technique to provide temporal isolation and low worst-case latency (WCL) bounds when cores access the shared LLC in multicore safety-critical systems. A typical approach to cache partitioning involves allocating a ...
- research-articleJanuary 2022
Cooperative Slack Management: Saving Energy of Multicore Processors by Trading Performance Slack Between QoS-Constrained Applications
ACM Transactions on Architecture and Code Optimization (TACO), Volume 19, Issue 2Article No.: 21, Pages 1–27https://doi.org/10.1145/3505559Processor resources can be adapted at runtime according to the dynamic behavior of applications to reduce the energy consumption of multicore processors without affecting the Quality-of-Service (QoS). To achieve this, an online resource management scheme ...
- research-articleJanuary 2022
- research-articleOctober 2021
UC-Check: Characterizing Micro-operation Caches in x86 Processors and Implications in Security and Performance
MICRO '21: MICRO-54: 54th Annual IEEE/ACM International Symposium on MicroarchitecturePages 550–564https://doi.org/10.1145/3466752.3480079The modern x86 processor (e.g., Intel, AMD) translates CISC-style x86 instructions to RISC-style micro operations (uops) as RISC pipelines are more efficient than CISC pipelines. However, this x86 decoding process requires complex hardware logic (i.e., ...
- research-articleJune 2021
Improving Lifetime of Non-Volatile Memory Caches by Logical Partitioning
GLSVLSI '21: Proceedings of the 2021 Great Lakes Symposium on VLSIPages 123–128https://doi.org/10.1145/3453688.3461488We are in an era of highly data-intensive applications, and the existing memory technologies are inadequate to meet their challenges. Non-Volatile Memories (NVMs) have emerged as a cost-effective alternative to the conventional SRAM based Last Level ...
- research-articleNovember 2021
Don't forget the I/O when allocating your LLC
ISCA '21: Proceedings of the 48th Annual International Symposium on Computer ArchitecturePages 112–125https://doi.org/10.1109/ISCA52012.2021.00018In modern server CPUs, last-level cache (LLC) is a critical hardware resource that exerts significant influence on the performance of the workloads, and how to manage LLC is a key to the performance isolation and QoS in the cloud with multi-tenancy. In ...
- research-articleMay 2021
DFShards: effective construction of MRCs online for non-stack algorithms
CF '21: Proceedings of the 18th ACM International Conference on Computing FrontiersPages 63–72https://doi.org/10.1145/3457388.3458810The Miss Ratio Curve (MRC) describes the cache miss ratio as a function of the cache size. It has various shapes that represent the data access behaviors of workloads in the cache. MRC is an effective tool to guide cache partitioning, but its real-time ...
- research-articleNovember 2019
Co-scheduling HPC workloads on cache-partitioned CMP platforms
International Journal of High Performance Computing Applications (SAGE-HPCA), Volume 33, Issue 6Pages 1221–1239https://doi.org/10.1177/1094342019846956With the recent advent of many-core architectures such as chip multiprocessors (CMPs), the number of processing units accessing a global shared memory is constantly increasing. Co-scheduling techniques are used to improve application throughput on such ...
- research-articleAugust 2019
LFOC: A Lightweight Fairness-Oriented Cache Clustering Policy for Commodity Multicores
ICPP '19: Proceedings of the 48th International Conference on Parallel ProcessingArticle No.: 14, Pages 1–10https://doi.org/10.1145/3337821.3337925Multicore processors constitute the main architecture choice for modern computing systems in different market segments. Despite their benefits, the contention that naturally appears when multiple applications compete for the use of shared resources ...
- research-articleApril 2019
Cache Reconfiguration Using Machine Learning for Vulnerability-aware Energy Optimization
ACM Transactions on Embedded Computing Systems (TECS), Volume 18, Issue 2Article No.: 15, Pages 1–24https://doi.org/10.1145/3309762Dynamic cache reconfiguration has been widely explored for energy optimization and performance improvement for single-core systems. Cache partitioning techniques are introduced for the shared cache in multicore systems to alleviate inter-core ...
- research-articleDecember 2018
SCORE: A Novel Scheme to Efficiently Cache Overlong ECCs in NAND Flash Memory
ACM Transactions on Architecture and Code Optimization (TACO), Volume 15, Issue 4Article No.: 60, Pages 1–25https://doi.org/10.1145/3291052Technology scaling and program/erase cycling result in an increasing bit error rate in NAND flash storage. Some solid state drives (SSDs) adopt overlong error correction codes (ECCs), whose redundancy size exceeds the spare area limit of flash pages, to ...
- research-articleApril 2018
DCAPS: dynamic cache allocation with partial sharing
EuroSys '18: Proceedings of the Thirteenth EuroSys ConferenceArticle No.: 13, Pages 1–15https://doi.org/10.1145/3190508.3190511In a multicore system, effective management of shared last level cache (LLC), such as hardware/software cache partitioning, has attracted significant research attention. Some eminent progress is that Intel introduced Cache Allocation Technology (CAT) to ...
- research-articleJanuary 2018
Co-scheduling Amdahl applications on cache-partitioned systems
International Journal of High Performance Computing Applications (SAGE-HPCA), Volume 32, Issue 1Pages 123–138https://doi.org/10.1177/1094342017710806Cache-partitioned architectures allow subsections of the shared last-level cache LLC to be exclusively reserved for some applications. This technique dramatically limits interactions between applications that are concurrently executing on a multicore ...
- research-articleNovember 2017
Exploring cache bypassing and partitioning for multi-tasking on GPUs
Graphics Processing Units (GPUs) computing has become ubiquitous for embedded system, evidenced by its wide adoption for various general purpose applications. As more and more applications are accelerated by GPUs, multi-tasking scenario starts to ...