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Eh?Placer: A High-Performance Modern Technology-Driven Placer

Published: 19 April 2016 Publication History

Abstract

The placement problem has become more complex and challenging due to a wide variety of complicated constraints imposed by modern process technologies. Some of the most challenging constraints and objectives were highlighted during the most recent ACM/IEEE International Symposium on Physical Design (ISPD) contests. In this article, the framework of Eh?Placer and its developed algorithms are elaborated, with the main focus on modern technology constraints and runtime. The technology constraints considered as part of Eh?Placer are fence region, target density, and detailed routability constraints. We present a complete description on how these constraints are considered in different stages of Eh?Placer. The results obtained from the contests indicate that Eh?Placer is able to efficiently handle modern technology constraints and ranks highly among top academic placement tools.

References

[1]
ACM/SIGDA. 2014. ISPD 2014 Detailed Routing-Driven Placement Contest. Retrieved from http://www.ispd.cc/contests/14/ispd2014_contest.html.
[2]
Charles Alpert, Zhuo Li, Gi-Joon Nam, Cliff N. Sze, Natarajan Viswanathan, and Samuel I. Ward. 2012. Placement: Hot or not? In Proc. of ICCAD. 283--290.
[3]
Mark de Berg, Otfried Cheong, Marc van Kreveld, and Mark Overmars. 2008. Computational Geometry: Algorithms and Applications (3rd ed.). Springer-Verlag. 307--320 pages.
[4]
Ulrich Brenner and Jens Vygen. 2004. Legalizing a placement with minimum total movement. IEEE TCAD 23, 12 (2004), 1597--1613.
[5]
Ismail S. Bustany, David Chinnery, Joseph R. Shinnerl, and Vladimir Yutsi. 2015. ISPD 2015 benchmarks with fence regions and routing blockages for detailed-routing-driven placement. In Proc. of ISPD. 157--164.
[6]
Cadence, Inc. 2009. LEF/DEF version 5.3-5.7 exchange format. Retrieved from http://www.si2.org/openeda.si2.org/projects/lefdef.
[7]
Tony F. Chan, Kenton Sze, Joseph R. Shinnerl, and Min Xie. 2007. mPL6: Enhanced multilevel mixed-size placement with congestion control. In Modern Circuit Placement, Gi-Joon Nam and Jason Cong (Eds.). Springer US, 247--288.
[8]
Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, and Yao-Wen Chang. 2008. NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints. IEEE TCAD 27 (July 2008), 1228--1240.
[9]
Minsik Cho, Haoxing Ren, Hua Xiang, and Ruchir Puri. 2010. History-based VLSI legalization using network flow. In Proc. of DAC. 286--291.
[10]
Jason Cong, Guojie Luo, Killiopi Tsota, and Bingjun Xiao. 2013. Optimizing routability in large-scale mixed-size placement. In Proc. of ASP-DAC. 441--446.
[11]
Ke-Ren Dai, Wen-Hao Liu, and Yih-Lang Li. 2012. NCTU-GR: Efficient simulated evolution-based rerouting and congestion-relaxed layer assignment on 3-d global routing. IEEE TVLSI 20, 3 (March 2012), 459--472.
[12]
Xu He, Tao Huang, Wing-Kai Chow, Jian Kuang, Ka-Chun Lam, Wenzan Cai, and Evangeline F. Y. Young. 2013. Ripple 2.0: High quality routability-driven placement via global router integration. In Proc. of DAC. 1--6.
[13]
John L. Hennessy and David A. Patterson. 2011. Computer Architecture: A Quantitative Approach (5th ed.). Morgan Kaufmann Publishers.
[14]
Jin Hu, Myung-Chul Kim, and Igor L. Markov. 2013. Taming the complexity of coordinated place and route. In Proc. of DAC. 150:1--150:7.
[15]
Chau-Chin Huang, Chien-Hsiung Chiou, Kai-Han Tseng, and Yao-Wen Chang. 2015. Detailed-routing-driven analytical standard-cell placement. In Proc. of ASP-DAC. 378--383.
[16]
Andrew B. Kahng, Igor L. Markov, and Sherief Reda. 2004. On legalization of row-based placements. In Proc. of GLSVLSI. 214--219.
[17]
Andrew B. Kahng and Qinke Wang. 2006. A faster implementation of aplace. In Proc. of ISPD. 218--220.
[18]
Ateen Khatkhate, Chen Li, Ameya R. Agnihotri, Mehmet C. Yildiz, Satoshi Ono, Cheng-Kok Koh, and Patrick H. Madden. 2004. Recursive bisection based mixed block placement. In Proc. of ISPD. 84--89.
[19]
Myung-Chul Kim, Jin Hu, Dong-Jin Lee, and Igor L. Markov. 2011. A SimPLR method for routability-driven placement. In Proc. of ICCAD. 67--73.
[20]
Myung-Chul Kim, Dongjin Lee, and Igor L. Markov. 2012a. SimPL: An effective placement algorithm. IEEE TCAD 31, 1 (2012), 50--60.
[21]
Myung-Chul Kim and Igor L. Markov. 2012. ComPLx: A competitive primal-dual lagrange optimization for global placement. In Proc. of DAC. 747--752.
[22]
Myung-Chul Kim, Natarajan Viswanathan, Charles J. Alpert, Igor L. Markov, and Shyam Ramji. 2012b. MAPLE: Multilevel adaptive placement for mixed-size designs. In Proc. of ISPD. 193--200.
[23]
Shuai Li and Cheng-kok Koh. 2014. MIP-based detailed placer for mixed-size circuits. In Proc. of ISPD. 11--18.
[24]
Tao Lin and Chris Chu. 2014. POLAR 2.0: An effective routability-driven placer. In Proc. of DAC. 1--6.
[25]
Tao Lin, Chris Chu, Joseph R. Shinnerl, Ismail Bustany, and Ivailo Nedelchev. 2015. POLAR: A high performance mixed-size wirelengh-driven placer with density constraints. IEEE TCAD 34, 3 (2015), 447--459.
[26]
Jingwei Lu, Pengwen Chen, Chin-Chih Chang, Lu Sha, Dennis Jen-Hsin Huang, Chin-Chi Teng, and Chung-Kuan Cheng. 2015. ePlace: Electrostatics-based placement using fast fourier transform and Nesterov’s method. ACM Trans. Des. Autom. Electron. Syst. 20 (March 2015), 17:1--17:34.
[27]
Qiang Ma and Evangeline F. Y. Young. 2010. Multivoltage floorplan design. IEEE TCAD 29, 4 (2010), 607--617.
[28]
Mentor Graphics, Inc. 2015. Olympus-SoC Place and Route for Advanced Node Designs. Technical Report. Retrieved from www.mentor.com/products/ic_nanometer_design/place-route/olympus-soc.
[29]
Gi-Joon Nam. 2006. ISPD 2006 placement contest: Benchmark suite and results. In Proc. of ISPD. 167--167.
[30]
Jorge Nocedal and Steve J. Wright. 2006. Numerical Optimization. Springer.
[31]
Min Pan, Natarajan Viswanathan, and Chris Chu. 2005. An efficient and effective detailed placement algorithm. In Proc. of ICCAD. 48--55.
[32]
Yousef Saad. 2003. Iterative Methods for Sparse Linear Systems (2nd ed.). Society for Industrial and Applied Mathematics, Philadelphia, PA.
[33]
Peter Spindler, Ulf Schlichtmann, and Frank M. Johannes. 2008a. Abacus: Fast legalization of standard cell circuits with minimal movement. In Proc. of ISPD. 47--53.
[34]
Peter Spindler, Ulf Schlichtmann, and Frank M. Johannes. 2008b. Kraftwerk2--a fast force-directed quadratic placement approach using an accurate net model. IEEE TCAD 27, 8 (2008), 1398--1411.
[35]
Natarajan Viswanathan, Min Pan, and Chris Chu. 2007. FastPlace 3.0: A fast multilevel quadratic placement algorithm with placement congestion control. In Proc. of ASP-DAC.
[36]
Chun-Kai Wang, Chuan-Chia Huang, Sean Shih-Ying Liu, Ching-Yu Chin, Sheng-Te Hu, Wei-Chen Wu, and Hung-Ming Chen. 2015. Closing the gap between global and detailed placement: Techniques for improving routability. In Proc. of ISPD. 149--156.
[37]
Laung-Terng Wang, Yao-Wen Chang, and Kwang-Ting Cheng. 2009. Electronic Design Automation: Synthesis, Verification, and Test. Elsevier Science.
[38]
Vladimir Yutsis, Ismail S. Bustany, David Chinnery, Joseph R. Shinnerl, and Wen-Hao Liu. 2014. ISPD 2014 benchmarks with sub-45Nm technology rules for detailed-routing-driven placement. In Proc. of ISPD. 161--168.
[39]
Wenxing Zhu, Jianli Chen, Zheng Peng, and Genghua Fan. 2015. Nonsmooth optimization method for VLSI global placement. IEEE TCAD 34, 4 (2015), 642--655.

Cited By

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  • (2024)Xplace: An Extremely Fast and Extensible Placement FrameworkIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.334629143:6(1872-1885)Online publication date: Jun-2024
  • (2024)ILPGRC: ILP-Based Global Routing Optimization With Cell MovementsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.330557943:1(352-365)Online publication date: 1-Jan-2024
  • (2023)CRP2.0: A Fast and Robust Cooperation between Routing and Placement in Advanced Technology NodesACM Transactions on Design Automation of Electronic Systems10.1145/359096228:5(1-42)Online publication date: 9-Sep-2023
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    Published In

    cover image ACM Transactions on Design Automation of Electronic Systems
    ACM Transactions on Design Automation of Electronic Systems  Volume 21, Issue 3
    Special Section on New Physical Design Techniques for the Next Generation Integration Technology and Regular Papers
    July 2016
    434 pages
    ISSN:1084-4309
    EISSN:1557-7309
    DOI:10.1145/2926747
    • Editor:
    • Naehyuck Chang
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    New York, NY, United States

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    Publication History

    Published: 19 April 2016
    Accepted: 01 January 2016
    Revised: 01 December 2015
    Received: 01 July 2015
    Published in TODAES Volume 21, Issue 3

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    Author Tags

    1. Region constraints
    2. placement
    3. target density

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    • Refereed

    Funding Sources

    • Alberta Innovates-Technology Futures (AITF)
    • Natural Sciences and Engineering Council of Canada (NSERC)
    • Compute/Calcul Canada and the Canadian Microelectronics Corporation (CMC)

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    Cited By

    View all
    • (2024)Xplace: An Extremely Fast and Extensible Placement FrameworkIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.334629143:6(1872-1885)Online publication date: Jun-2024
    • (2024)ILPGRC: ILP-Based Global Routing Optimization With Cell MovementsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.330557943:1(352-365)Online publication date: 1-Jan-2024
    • (2023)CRP2.0: A Fast and Robust Cooperation between Routing and Placement in Advanced Technology NodesACM Transactions on Design Automation of Electronic Systems10.1145/359096228:5(1-42)Online publication date: 9-Sep-2023
    • (2023)An accelerated modulus-based matrix splitting iteration method for mixed-size cell circuits legalizationIntegration, the VLSI Journal10.1016/j.vlsi.2022.08.01088:C(20-31)Online publication date: 1-Jan-2023
    • (2022)CR&PProceedings of the 2022 Conference & Exhibition on Design, Automation & Test in Europe10.5555/3539845.3540030(772-777)Online publication date: 14-Mar-2022
    • (2022)CR&P: An Efficient Co-operation between Routing and Placement2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE54114.2022.9774530(772-777)Online publication date: 14-Mar-2022
    • (2022)A Machine Learning Approach for Accelerating SimPL-Based Global Placement for FPGA'sProceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding10.1145/3557988.3569714(1-7)Online publication date: 3-Nov-2022
    • (2022)XplaceProceedings of the 59th ACM/IEEE Design Automation Conference10.1145/3489517.3530485(1309-1314)Online publication date: 10-Jul-2022
    • (2022)A Robust Two-Step Modulus-Based Matrix Splitting Iteration Method for Mixed-Size Cell Circuit Legalization ProblemJournal of Circuits, Systems and Computers10.1142/S021812662350129332:08Online publication date: 19-Nov-2022
    • (2022)Deep Learning Framework for PlacementMachine Learning Applications in Electronic Design Automation10.1007/978-3-031-13074-8_9(221-245)Online publication date: 10-Aug-2022
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