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A distributed timing analysis framework for large designs

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Natesan VenkateswaranAuthors Info & Claims

DAC '16: Proceedings of the 53rd Annual Design Automation Conference

Article No.: 116, Pages 1 - 6

https://doi.org/10.1145/2897937.2897959

Published: 05 June 2016 Publication History

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Abstract

Given ever-increasing circuit complexities, recent trends are driving the requirement for distributed timing analysis (DTA) in electronic design automation (EDA) tools. However, DTA has received little research attention so far and remains a critical problem. In this paper, we introduce a DTA framework for large designs. Our framework supports (1) general design partitions in distributed file systems, (2) non-blocking IO with event-driven loop for effective communication and computation overlap, and (3) an efficient messaging interface between application and network layers. The effectiveness and scalability of our framework has been evaluated on large hierarchical industry designs over a cluster with hundreds of machines.

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Cited By

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Chiu CXiong ZGuo ZHuang TLin Y(2024)An Efficient Task-Parallel Pipeline Programming FrameworkProceedings of the International Conference on High Performance Computing in Asia-Pacific Region10.1145/3635035.3635037(95-106)Online publication date: 18-Jan-2024
https://dl.acm.org/doi/10.1145/3635035.3635037
Huang TZhang BLin DChiu CHui-Ru Jiang IPosser G(2024)Parallel and Heterogeneous Timing Analysis: Partition, Algorithm, and SystemProceedings of the 2024 International Symposium on Physical Design10.1145/3626184.3635278(51-59)Online publication date: 12-Mar-2024
https://dl.acm.org/doi/10.1145/3626184.3635278
Chang CChiu CZhang BHuang T(2024)Incremental Critical Path Generation for Dynamic Graphs2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI61997.2024.00150(771-774)Online publication date: 1-Jul-2024
https://doi.org/10.1109/ISVLSI61997.2024.00150
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Published In

DAC '16: Proceedings of the 53rd Annual Design Automation Conference

June 2016

1048 pages

ISBN:9781450342360

DOI:10.1145/2897937

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 June 2016

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DAC '16

DAC '16: The 53rd Annual Design Automation Conference 2016

June 5 - 9, 2016

Texas, Austin

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Chiu CXiong ZGuo ZHuang TLin Y(2024)An Efficient Task-Parallel Pipeline Programming FrameworkProceedings of the International Conference on High Performance Computing in Asia-Pacific Region10.1145/3635035.3635037(95-106)Online publication date: 18-Jan-2024
https://dl.acm.org/doi/10.1145/3635035.3635037
Huang TZhang BLin DChiu CHui-Ru Jiang IPosser G(2024)Parallel and Heterogeneous Timing Analysis: Partition, Algorithm, and SystemProceedings of the 2024 International Symposium on Physical Design10.1145/3626184.3635278(51-59)Online publication date: 12-Mar-2024
https://dl.acm.org/doi/10.1145/3626184.3635278
Chang CChiu CZhang BHuang T(2024)Incremental Critical Path Generation for Dynamic Graphs2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI61997.2024.00150(771-774)Online publication date: 1-Jul-2024
https://doi.org/10.1109/ISVLSI61997.2024.00150
Chiu CHuang T(2024)An Experimental Study of Dynamic Task Graph Parallelism for Large-Scale Circuit Analysis Workloads2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI61997.2024.00149(766-770)Online publication date: 1-Jul-2024
https://doi.org/10.1109/ISVLSI61997.2024.00149
Morchdi CChiu CZhou YHuang T(2024)A Resource-efficient Task Scheduling System using Reinforcement Learning : Invited Paper2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC58780.2024.10473960(89-95)Online publication date: 22-Jan-2024
https://doi.org/10.1109/ASP-DAC58780.2024.10473960
Tu KTang XYu CJosipović LChu ZTu KTang XYu CJosipović LChu Z(2024)Performance (Timing) AnalysisFPGA EDA10.1007/978-981-99-7755-0_5(73-78)Online publication date: 1-Feb-2024
https://doi.org/10.1007/978-981-99-7755-0_5
Guo ZHuang TLin Y(2023)Accelerating Static Timing Analysis Using CPU–GPU Heterogeneous ParallelismIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.328626142:12(4973-4984)Online publication date: Dec-2023
https://doi.org/10.1109/TCAD.2023.3286261
Guo GHuang TLin YGuo ZYellapragada SWong M(2023)A GPU-Accelerated Framework for Path-Based Timing AnalysisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.327227442:11(4219-4232)Online publication date: Nov-2023
https://doi.org/10.1109/TCAD.2023.3272274
Chiu CLin DHuang T(2023)Invited Paper: Programming Dynamic Task Parallelism for Heterogeneous EDA Algorithms2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323760(1-8)Online publication date: 28-Oct-2023
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Huang TLin DLin YLin C(2022)Taskflow: A General-Purpose Parallel and Heterogeneous Task Programming SystemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.308250741:5(1448-1452)Online publication date: May-2022
https://doi.org/10.1109/TCAD.2021.3082507
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