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Design Rule Management and its Applications in 15nm FreePDK Technology

Published: 29 March 2015 Publication History

Abstract

This paper reviews the industry practice of using the design rule manual (DRM) for documenting semiconductor manufacturing limitations and how these are translated to design rule check (DRC) decks. The fundamental flaws in the current paradigm are shown as well as the resulting negative impact on the industry. We will then describe a new paradigm to document and manage design rules that eliminates these flaws and closes the loop between design and manufacturing. We will illustrate the talk with application of the methodology for design rule management and checks performed during the development of the Open Cell Library (OCL) as part of the 15nm FreePDK technology.

References

[1]
Carver Mead and Lynn Conway. Introduction to VLSI systems. Vol. 1080. Reading, MA: Addison-Wesley, 1980.
[2]
Neil Weste and David Harris. CMOS VLSI Design: A Circuits and Systems Perspective. Addison-Wesley; 4 edition, 2010.
[3]
Y. Z. Liao and C. K. Wong. 1983. An algorithm to compact a VLSI symbolic layout with mixed constraints. In Proceedings of the 20th Design Automation Conference (DAC '83). IEEE Press, Piscataway, NJ, USA, 107--112.
[4]
Losleben, P.; Thompson, K., "Topological Analysis for VLSI Circuits," Design Automation, 1979. 16th Conference on, vol., no., pp. 461--473, 25-27 June 1979.
[5]
Smith, R.; Joy, R., "Computer aided design tools for VLSI," Solid-State Circuits Conference. Digest of Technical Papers. 1980 IEEE International, vol. XXIII, no., pp. 193--193, 13-15 Feb. 1980.
[6]
Jin-Fuw Lee, "A new framework of design rules for compaction of VLSI layouts," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 7, no. 11, pp.1195--1204, Nov 1988.
[7]
McGrath, E. J.; Whitney, T., "Design Integrity and Immunity Checking: A New Look at Layout Verification and Design Rule Checking," Design Automation, 1980. 17th Conference on, vol., no., pp. 263--268, 23-25 June 1980.
[8]
Vito Dai; Jie Yang; Norma Rodriguez; Luigi Capodieci; DRC Plus: augmenting standard DRC with pattern matching on 2D geometries. Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 65210A (March 28, 2007).
[9]
Raina, R. What is dfm & dfy and why should i care? IEEE Test Conference, 2006. ITC'06, pp. 1--9.
[10]
Rick Merritt, Synopsys bullish despite rising chip complexity Article, EETimes designlines March 26 2013 http://www.eetimes.com/document.asp?doc_id=1280659
[11]
Kirti N Bhanushali. May 2014. Design Rule Development for FreePDK15: An Open Source Predictive Process Design Kit for 15nm FinFET Devices. Thesis, North Carolina State University. http://www.lib.ncsu.edu/resolver/1840.16/9519
[12]
Kirti Bhanushali and Rhett Davis. "FreePDK15: An Open-Source Predictive Process Design Kit for 15nm FinFET Technology", ISPD 2015.
[13]
Mayler Martins, Jody Matos, Renato Ribas, Andre Reis, Guilherme Schlinker, Lucio Rech and Jens Michelsen. "Open Cell Library in 15nm FreePDK Technology", ISPD 2015.
[14]
Jody Matos, Augusto Neutzling, Renato Ribas and Andre Reis. "A Benchmark Suite to Jointly Consider Logic Synthesis and Physical Design", ISPD 2015.

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cover image ACM Conferences
ISPD '15: Proceedings of the 2015 Symposium on International Symposium on Physical Design
March 2015
204 pages
ISBN:9781450333993
DOI:10.1145/2717764
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

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Publication History

Published: 29 March 2015

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Author Tags

  1. design rule check
  2. design rules
  3. electronic design automation
  4. integrated circuits
  5. physical design verification
  6. semiconductor technology

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ISPD'15
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ISPD'15: International Symposium on Physical Design
March 29 - April 1, 2015
California, Monterey, USA

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ISPD '15 Paper Acceptance Rate 14 of 37 submissions, 38%;
Overall Acceptance Rate 62 of 172 submissions, 36%

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ISPD '25
International Symposium on Physical Design
March 16 - 19, 2025
Austin , TX , USA

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