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GhostRider: A Hardware-Software System for Memory Trace Oblivious Computation

Published: 14 March 2015 Publication History

Abstract

This paper presents a new, co-designed compiler and architecture called GhostRider for supporting privacy preserving computation in the cloud. GhostRider ensures all programs satisfy a property called memory-trace obliviousness (MTO): Even an adversary that observes memory, bus traffic, and access times while the program executes can learn nothing about the program's sensitive inputs and outputs. One way to achieve MTO is to employ Oblivious RAM (ORAM), allocating all code and data in a single ORAM bank, and to also disable caches or fix the rate of memory traffic. This baseline approach can be inefficient, and so GhostRider's compiler uses a program analysis to do better, allocating data to non-oblivious, encrypted RAM (ERAM) and employing a scratchpad when doing so will not compromise MTO. The compiler can also allocate to multiple ORAM banks, which sometimes significantly reduces access times.We have formalized our approach and proved it enjoys MTO. Our FPGA-based hardware prototype and simulation results show that GhostRider significantly outperforms the baseline strategy.

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Published In

cover image ACM SIGPLAN Notices
ACM SIGPLAN Notices  Volume 50, Issue 4
ASPLOS '15
April 2015
676 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/2775054
  • Editor:
  • Andy Gill
Issue’s Table of Contents
  • cover image ACM Conferences
    ASPLOS '15: Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems
    March 2015
    720 pages
    ISBN:9781450328357
    DOI:10.1145/2694344
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Publication History

Published: 14 March 2015
Published in SIGPLAN Volume 50, Issue 4

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  1. memory trace obliviousness
  2. oblivious ram
  3. secure type system

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Cited By

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  • (2024)Interface-Based Side Channel in TEE-Assisted Networked ServicesIEEE/ACM Transactions on Networking10.1109/TNET.2023.329401932:1(613-626)Online publication date: 1-Feb-2024
  • (2024)Camo-DNN: Layer Camouflaging to Protect DNNs against Timing Side-Channel Attacks2024 IEEE 30th International Symposium on On-Line Testing and Robust System Design (IOLTS)10.1109/IOLTS60994.2024.10616065(1-7)Online publication date: 3-Jul-2024
  • (2024)Formal Hardware/Software Models for Cache Locking Enabling Fast and Secure CodeComputer Security – ESORICS 202410.1007/978-3-031-70896-1_8(153-173)Online publication date: 6-Sep-2024
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  • (2023)Preventing Coherence State Side Channel Leaks Using TimeCacheIEEE Transactions on Computers10.1109/TC.2022.320992272:2(374-385)Online publication date: 1-Feb-2023
  • (2023)Oblivious RAM-Based Secure ProcessorsEncyclopedia of Cryptography, Security and Privacy10.1007/978-3-642-27739-9_1553-1(1-3)Online publication date: 30-Apr-2023
  • (2022)AdoreProceedings of the VLDB Endowment10.14778/3574245.357426716:4(842-855)Online publication date: 1-Dec-2022
  • (2022)NeuralD: Detecting Indistinguishability Violations of Oblivious RAM With Neural DistinguishersIEEE Transactions on Information Forensics and Security10.1109/TIFS.2022.315527417(982-997)Online publication date: 2022
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