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- articleJune 2018
An open-source realtime computational platform (short WIP paper)
ACM SIGPLAN Notices (SIGPLAN), Volume 53, Issue 6Pages 109–112https://doi.org/10.1145/3299710.3211344Systems neuroscience studies involving in-vivo models often require realtime data processing. In these studies, many events must be monitored and processed quickly, including behavior of the subject (e.g., movement of a limb) or features of neural data (...
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LCTES 2018: Proceedings of the 19th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems: ISBN 9781450358033 - articleJune 2018
JSCore: architectural support for accelerating JavaScript execution (short WIP paper)
ACM SIGPLAN Notices (SIGPLAN), Volume 53, Issue 6Pages 104–108https://doi.org/10.1145/3299710.3211343JavaScript has seen meteoric growth in popularity as it has in- creasingly become the language of choice for developers, both for front-end web development and server code development through various JavaScript frameworks and Node.js. Part of the reason ...
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LCTES 2018: Proceedings of the 19th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems: ISBN 9781450358033 Verification of coarse-grained reconfigurable arrays through random test programs
We propose and evaluate a framework to test the functional correctness of coarse-grained reconfigurable array (CGRA) processors for pre-silicon verification and post-silicon validation. To reflect the reconfigurable nature of CGRAs, an architectural ...
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LCTES 2018: Proceedings of the 19th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems: ISBN 9781450358033- articleJune 2018
Optimizing RAID/SSD controllers with lifetime extension for flash-based SSD array
Flash-based SSD RAID arrays are increasingly being deployed in data centers. Compared with HDD arrays, SSD arrays drastically enhance storage density and I/O performance, and reduce power and rack space. Nevertheless, SSDs suffer aging issues. Though ...
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LCTES 2018: Proceedings of the 19th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems: ISBN 9781450358033 - articleJune 2018
Transparent standby for low-power, resource-constrained embedded systems: a programming language-based approach (short WIP paper)
Standby efficiency for connected devices is one of the priorities of the G20’s Energy Efficiency Action Plan. We propose transparent programming language mechanisms to enforce that applications remain in the deepest standby modes for the longest periods ...
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LCTES 2018: Proceedings of the 19th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems: ISBN 9781450358033 -
Adaptive deep learning model selection on embedded systems
The recent ground-breaking advances in deep learning networks (DNNs) make them attractive for embedded systems. However, it can take a long time for DNNs to make an inference on resource-limited embedded devices. Offloading the computation into the ...
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LCTES 2018: Proceedings of the 19th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems: ISBN 9781450358033A memory-bounded, deterministic and terminating semantics for the synchronous programming language Céu
Céu is a synchronous programming language for embedded soft real-time systems. It focuses on control-flow safety features, such as safe shared-memory concurrency and safe abortion of lines of execution, while enforcing memory bounded, deterministic, and ...
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LCTES 2018: Proceedings of the 19th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems: ISBN 9781450358033- articleJune 2018
Hardware-software co-optimization of memory management in dynamic languages
Dynamic programming languages are becoming increasingly popular, yet often show a significant performance slowdown compared to static languages. In this paper, we study the performance overhead of automatic memory management in dynamic languages. We ...
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ISMM 2018: Proceedings of the 2018 ACM SIGPLAN International Symposium on Memory Management: ISBN 9781450358019 - research-articleJune 2018
Partial control-flow linearization
ACM SIGPLAN Notices (SIGPLAN), Volume 53, Issue 4Pages 543–556https://doi.org/10.1145/3296979.3192413If-conversion is a fundamental technique for vectorization. It accounts for the fact that in a SIMD program, several targets of a branch might be executed because of divergence. Especially for irregular data-parallel workloads, it is crucial to avoid if-...
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PLDI 2018: Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation: ISBN 9781450356985 VeriPhy: verified controller executables from verified cyber-physical system models
ACM SIGPLAN Notices (SIGPLAN), Volume 53, Issue 4Pages 617–630https://doi.org/10.1145/3296979.3192406We present VeriPhy, a verified pipeline which automatically transforms verified high-level models of safety-critical cyber-physical systems (CPSs) in differential dynamic logic (dL) to verified controller executables. VeriPhy proves that all safety ...
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PLDI 2018: Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation: ISBN 9781450356985- research-articleJune 2018
Write-rationing garbage collection for hybrid memories
Emerging Non-Volatile Memory (NVM) technologies offer high capacity and energy efficiency compared to DRAM, but suffer from limited write endurance and longer latencies. Prior work seeks the best of both technologies by combining DRAM and NVM in hybrid ...
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PLDI 2018: Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation: ISBN 9781450356985 - research-articleJune 2018
Enhancing computation-to-core assignment with physical location information
ACM SIGPLAN Notices (SIGPLAN), Volume 53, Issue 4Pages 312–327https://doi.org/10.1145/3296979.3192386Going beyond a certain number of cores in modern architectures requires an on-chip network more scalable than conventional buses. However, employing an on-chip network in a manycore system (to improve scalability) makes the latencies of the data ...
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PLDI 2018: Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation: ISBN 9781450356985 - research-articleJune 2018
iReplayer: in-situ and identical record-and-replay for multithreaded applications
ACM SIGPLAN Notices (SIGPLAN), Volume 53, Issue 4Pages 344–358https://doi.org/10.1145/3296979.3192380Reproducing executions of multithreaded programs is very challenging due to many intrinsic and external non-deterministic factors. Existing RnR systems achieve significant progress in terms of performance overhead, but none targets the in-situ setting, ...
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PLDI 2018: Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation: ISBN 9781450356985 - research-articleJune 2018
Mapping spiking neural networks onto a manycore neuromorphic architecture
We present a compiler for Loihi, a novel manycore neuromorphic processor that features a programmable, on-chip learning engine for training and executing spiking neural networks (SNNs). An SNN is distinguished from other neural networks in that (1) its ...
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PLDI 2018: Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation: ISBN 9781450356985 - research-articleJune 2018
Persistency for synchronization-free regions
Nascent persistent memory (PM) technologies promise the performance of DRAM with the durability of disk, but how best to integrate them into programming systems remains an open question. Recent work extends language memory models with a persistency ...
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PLDI 2018: Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation: ISBN 9781450356985 - tutorialMarch 2018
An Analysis of x86-64 Inline Assembly in C Programs
C codebases frequently embed nonportable and unstandardized elements such as inline assembly code. Such elements are not well understood, which poses a problem to tool developers who aspire to support C code. This paper investigates the use of x86-64 ...
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VEE '18: Proceedings of the 14th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments: ISBN 9781450355797 - research-articleMarch 2018
Slim NoC: A Low-Diameter On-Chip Network Topology for High Energy Efficiency and Scalability
- Maciej Besta,
- Syed Minhaj Hassan,
- Sudhakar Yalamanchili,
- Rachata Ausavarungnirun,
- Onur Mutlu,
- Torsten Hoefler
Emerging chips with hundreds and thousands of cores require networks with unprecedented energy/area efficiency and scalability. To address this, we propose Slim NoC (SN): a new on-chip network design that delivers significant improvements in efficiency ...
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ASPLOS '18: Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems: ISBN 9781450349116 - research-articleMarch 2018
NEOFog: Nonvolatility-Exploiting Optimizations for Fog Computing
- Kaisheng Ma,
- Xueqing Li,
- Mahmut Taylan Kandemir,
- Jack Sampson,
- Vijaykrishnan Narayanan,
- Jinyang Li,
- Tongda Wu,
- Zhibo Wang,
- Yongpan Liu,
- Yuan Xie
ACM SIGPLAN Notices (SIGPLAN), Volume 53, Issue 2Pages 782–796https://doi.org/10.1145/3296957.3177154Nonvolatile processors have emerged as one of the promising solutions for energy harvesting scenarios, among which Wireless Sensor Networks (WSN) provide some of the most important applications. In a typical distributed sensing system, due to difference ...
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ASPLOS '18: Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems: ISBN 9781450349116 - research-articleMarch 2018
Quantum Computing is Getting Real: Architecture, PL, and OS Roles in Closing the Gap between Quantum Algorithms and Machines
Quantum computing is at an inflection point, where 50-qubit (quantum bit) machines have been built, 100-qubit machines are just around the corner, and even 1000-qubit machines are perhaps only a few years away. These machines have the potential to ...
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ASPLOS '18: Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems: ISBN 9781450349116 - research-articleMarch 2018
VIBNN: Hardware Acceleration of Bayesian Neural Networks
ACM SIGPLAN Notices (SIGPLAN), Volume 53, Issue 2Pages 476–488https://doi.org/10.1145/3296957.3173212Bayesian Neural Networks (BNNs) have been proposed to address the problem of model uncertainty in training and inference. By introducing weights associated with conditioned probability distributions, BNNs are capable of resolving the overfitting issue ...
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ASPLOS '18: Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems: ISBN 9781450349116