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To SAT or Not to SAT: Scalable Exploration of Functional Dependency

Published: 01 April 2010 Publication History

Abstract

Functional dependency is concerned with rewriting a Boolean function f as a function h over a set of base functions {g_1, \ldots, g_n}, i.e., f = h(g_1, \ldots, g_n). It plays an important role in many aspects of electronic design automation (EDA). Prior approaches to the exploration of functional dependency are based on binary decision diagrams (BDDs), which may not be easily scalable to large designs. This paper formulates both single-output and multiple-output functional dependencies as satisfiability (SAT) solving and exploits extensively the capability of a modern SAT solver. Thereby, functional dependency can be detected effectively through incremental SAT solving, and the dependency function h, if it exists, is obtained through Craig interpolation. The proposed method enables 1) scalable detection of functional dependency, 2) fast enumeration of dependency function under a large set of candidate base functions, and 3) potential application to large-scale logic synthesis and formal verification. Experimental results show that the proposed method is far superior to prior work and scales well in dealing with the largest ISCAS and ITC benchmark circuits with up to 200K gates.

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  • (2020)Engineering change order for combinational and sequential design rectificationProceedings of the 23rd Conference on Design, Automation and Test in Europe10.5555/3408352.3408519(726-731)Online publication date: 9-Mar-2020
  • (2020)Formal Verification of ECCs for Memories Using ACL2Journal of Electronic Testing: Theory and Applications10.1007/s10836-020-05904-236:5(643-663)Online publication date: 1-Oct-2020
  • (2018)Cost-aware patch generation for multi-target function rectification of engineering change ordersProceedings of the 55th Annual Design Automation Conference10.1145/3195970.3196017(1-6)Online publication date: 24-Jun-2018
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Information & Contributors

Information

Published In

cover image IEEE Transactions on Computers
IEEE Transactions on Computers  Volume 59, Issue 4
April 2010
143 pages

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 April 2010

Author Tags

  1. Automatic synthesis
  2. design aids
  3. logic design
  4. optimization.

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Cited By

View all
  • (2020)Engineering change order for combinational and sequential design rectificationProceedings of the 23rd Conference on Design, Automation and Test in Europe10.5555/3408352.3408519(726-731)Online publication date: 9-Mar-2020
  • (2020)Formal Verification of ECCs for Memories Using ACL2Journal of Electronic Testing: Theory and Applications10.1007/s10836-020-05904-236:5(643-663)Online publication date: 1-Oct-2020
  • (2018)Cost-aware patch generation for multi-target function rectification of engineering change ordersProceedings of the 55th Annual Design Automation Conference10.1145/3195970.3196017(1-6)Online publication date: 24-Jun-2018
  • (2016)Resource-aware functional ECO patch generationProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972050(1036-1041)Online publication date: 14-Mar-2016
  • (2015)Property-Directed Synthesis of Reactive Systems from Safety SpecificationsProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840930(794-801)Online publication date: 2-Nov-2015
  • (2015)Scalable sequence-constrained retention register minimization in power gating designProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744905(1-6)Online publication date: 7-Jun-2015
  • (2014)Constrained interpolation for guided logic synthesisProceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design10.5555/2691365.2691459(462-469)Online publication date: 3-Nov-2014
  • (2013)Synthesis of feedback decoders for initialized encodersProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488794(1-6)Online publication date: 29-May-2013
  • (2012)New & improved models for SAT-based bi-decompositionProceedings of the great lakes symposium on VLSI10.1145/2206781.2206817(141-146)Online publication date: 3-May-2012
  • (2012)When boolean satisfiability meets gaussian elimination in a simplex wayProceedings of the 24th international conference on Computer Aided Verification10.1007/978-3-642-31424-7_31(410-426)Online publication date: 7-Jul-2012
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