research-article

SI-TM: reducing transactional memory abort rates through snapshot isolation

Authors:

David Cheriton,

Amin Firoozshahian,

John P. StevensonAuthors Info & Claims

ACM SIGPLAN Notices, Volume 49, Issue 4

Pages 383 - 398

https://doi.org/10.1145/2644865.2541952

Published: 24 February 2014 Publication History

Abstract

Transactional memory represents an attractive conceptual model for programming concurrent applications. Unfortunately, high transaction abort rates can cause significant performance degradation. Conventional transactional memory realizations not only pessimistically abort transactions on every read-write conflict but also because of false sharing, cache evictions, TLB misses, page faults and interrupts. Consequently, the use of transactions needs to be restricted to a very small number of operations to achieve predictable performance, thereby, limiting its benefit to programming simplification. In this paper, we investigate snapshot isolation transactional memory in which transactions operate on memory snapshots that always guarantee consistent reads. By exploiting snapshots, an established database model of transactions, transactions can ignore read-write conflicts and only need to abort on write-write conflicts. Our implementation utilizes a memory controller that supports multiversion memory, to efficiently support snapshotting in hardware.We show that snapshot isolation can reduce the number of aborts in some cases by three orders of magnitude and improve performance by up to 20x.

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Cited By

Raad ALahav OVafeiadis V(2018)On Parallel Snapshot Isolation and Release/Acquire ConsistencyProgramming Languages and Systems10.1007/978-3-319-89884-1_33(940-967)Online publication date: 14-Apr-2018
https://doi.org/10.1007/978-3-319-89884-1_33
Cardoso DFoss LDu Bois A(2022)Exploring Opacity Software Transactional Memory in Haskell through Graph TransformationProceedings of the XXVI Brazilian Symposium on Programming Languages10.1145/3561320.3561325(15-23)Online publication date: 6-Oct-2022
https://dl.acm.org/doi/10.1145/3561320.3561325
Xu YYe CSolihin YShen XSalapura VZahran MChong FTang L(2022)FFCCDProceedings of the 49th Annual International Symposium on Computer Architecture10.1145/3470496.3527406(274-288)Online publication date: 18-Jun-2022
https://dl.acm.org/doi/10.1145/3470496.3527406
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Index Terms

SI-TM: reducing transactional memory abort rates through snapshot isolation
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

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SI-TM: reducing transactional memory abort rates through snapshot isolation
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Information & Contributors

Information

Published In

cover image ACM SIGPLAN Notices

ACM SIGPLAN Notices Volume 49, Issue 4

ASPLOS '14

April 2014

729 pages

ISSN:0362-1340

EISSN:1558-1160

DOI:10.1145/2644865

Editors:
Mark W. Bailey
Hamilton College, Clinton, NY
,
Rajeev Balasubramonian
University of Utah
,
Al Davis
University of Utah
,
Sarita Adve
University of Illinois at Urbana-Champ

Issue’s Table of Contents

ASPLOS '14: Proceedings of the 19th international conference on Architectural support for programming languages and operating systems
February 2014
780 pages
ISBN:9781450323055
DOI:10.1145/2541940
General Chairs:
Rajeev Balasubramonian
University of Utah
,
Al Davis
University of Utah
,
Program Chair:
Sarita Adve
University of Illinois at Urbana-Champ

Copyright © 2014 ACM.

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Publication History

Published: 24 February 2014

Published in SIGPLAN Volume 49, Issue 4

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Cited By

Raad ALahav OVafeiadis V(2018)On Parallel Snapshot Isolation and Release/Acquire ConsistencyProgramming Languages and Systems10.1007/978-3-319-89884-1_33(940-967)Online publication date: 14-Apr-2018
https://doi.org/10.1007/978-3-319-89884-1_33
Cardoso DFoss LDu Bois A(2022)Exploring Opacity Software Transactional Memory in Haskell through Graph TransformationProceedings of the XXVI Brazilian Symposium on Programming Languages10.1145/3561320.3561325(15-23)Online publication date: 6-Oct-2022
https://dl.acm.org/doi/10.1145/3561320.3561325
Xu YYe CSolihin YShen XSalapura VZahran MChong FTang L(2022)FFCCDProceedings of the 49th Annual International Symposium on Computer Architecture10.1145/3470496.3527406(274-288)Online publication date: 18-Jun-2022
https://dl.acm.org/doi/10.1145/3470496.3527406
Titos-Gil RFernandez Pascual RRos AAcacio M(2021)DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional MemoryIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2021.3085210(1-1)Online publication date: 2021
https://doi.org/10.1109/TPDS.2021.3085210
Shimchenko MTitos-Gil RFernández-Pascual RAcacio MKaxiras SRos AJimborean A(2021)Analysing software prefetching opportunities in hardware transactional memoryThe Journal of Supercomputing10.1007/s11227-021-03897-zOnline publication date: 2-Jun-2021
https://doi.org/10.1007/s11227-021-03897-z
Attiya HFatourou PHans SKanellou E(2021)Staleness and Local Progress in Transactional MemoryNetworked Systems10.1007/978-3-030-67087-0_15(227-243)Online publication date: 14-Jan-2021
https://doi.org/10.1007/978-3-030-67087-0_15
Atserias AMüller M(2020)Automating Resolution is NP-HardJournal of the ACM10.1145/340947267:5(1-17)Online publication date: 1-Sep-2020
https://dl.acm.org/doi/10.1145/3409472
Blelloch GGu YShun JSun Y(2020)Parallelism in Randomized Incremental AlgorithmsJournal of the ACM10.1145/340281967:5(1-27)Online publication date: 19-Sep-2020
https://dl.acm.org/doi/10.1145/3402819
Zhuk D(2020)A Proof of the CSP Dichotomy ConjectureJournal of the ACM10.1145/340202967:5(1-78)Online publication date: 26-Aug-2020
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Baader FBorgwardt SKoopmann POzaki AThost V(2020)Metric Temporal Description Logics with Interval-Rigid NamesACM Transactions on Computational Logic10.1145/339944321:4(1-46)Online publication date: 11-Aug-2020
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