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RapidMRC: approximating L2 miss rate curves on commodity systems for online optimizations

Published: 07 March 2009 Publication History

Abstract

Miss rate curves (MRCs) are useful in a number of contexts. In our research, online L2 cache MRCs enable us to dynamically identify optimal cache sizes when cache-partitioning a shared-cache multicore processor. Obtaining L2 MRCs has generally been assumed to be expensive when done in software and consequently, their usage for online optimizations has been limited. To address these problems and opportunities, we have developed a low-overhead software technique to obtain L2 MRCs online on current processors, exploiting features available in their performance monitoring units so that no changes to the application source code or binaries are required. Our technique, called RapidMRC, requires a single probing period of roughly 221 million processor cycles (147 ms), and subsequently 124 million cycles (83 ms) to process the data. We demonstrate its accuracy by comparing the obtained MRCs to the actual L2 MRCs of 30 applications taken from SPECcpu2006, SPECcpu2000, and SPECjbb2000. We show that RapidMRC can be applied to sizing cache partitions, helping to achieve performance improvements of up to 27%.

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Information

Published In

cover image ACM SIGARCH Computer Architecture News
ACM SIGARCH Computer Architecture News  Volume 37, Issue 1
ASPLOS 2009
March 2009
346 pages
ISSN:0163-5964
DOI:10.1145/2528521
Issue’s Table of Contents
  • cover image ACM Conferences
    ASPLOS XIV: Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
    March 2009
    358 pages
    ISBN:9781605584065
    DOI:10.1145/1508244
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 07 March 2009
Published in SIGARCH Volume 37, Issue 1

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Author Tags

  1. cache management
  2. cache partitioning
  3. chip multiprocessor
  4. dynamic optimization
  5. hardware performance counters
  6. miss rate curve
  7. multicore processor
  8. online optimization
  9. performance monitoring unit
  10. shared cache
  11. shared cache management

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Cited By

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  • (2020)Efficient miss ratio curve computation for heterogeneous content popularityProceedings of the 2020 USENIX Conference on Usenix Annual Technical Conference10.5555/3489146.3489197(741-751)Online publication date: 15-Jul-2020
  • (2020)Page Reusability-Based Cache Partitioning for Multi-Core SystemsIEEE Transactions on Computers10.1109/TC.2020.296806669:6(812-818)Online publication date: 1-Jun-2020
  • (2020)Huge Page Friendly Virtualized Memory ManagementJournal of Computer Science and Technology10.1007/s11390-020-9693-035:2(433-452)Online publication date: 27-Mar-2020
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