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Tomahawk: Parallelism and heterogeneity in communications signal processing MPSoCs

Authors:

Benedikt Noethen,

Torsten Limberg,

Gerhard FettweisAuthors Info & Claims

ACM Transactions on Embedded Computing Systems (TECS), Volume 13, Issue 3s

Article No.: 107, Pages 1 - 24

https://doi.org/10.1145/2517087

Published: 28 March 2014 Publication History

Abstract

Heterogeneity and parallelism in MPSoCs for 4G (and beyond) communications signal processing are inevitable in order to meet stringent power constraints and performance requirements. The question arises on how to cope with the problem of system programmability and runtime management incurred by the statically or even dynamically varying number and type of processing elements. This work addresses this challenge by proposing the concept of a heterogeneous many-core platform called Tomahawk. Apart from the definition of the system architecture, in this approach a unified framework including a model of computation, a programming interface and a dedicated runtime management unit called CoreManager is proposed. The increase of system complexity in terms of application parallelism and number of resources may lead to a dramatic increase of the management costs, hence causing performance degradation. For this reason, the efficient implementation of the CoreManager becomes a major issue in system design. This work compares the performance and capabilities of various CoreManager HW/SW solutions, based on ASIC, RISC and ASIP paradigms. The results demonstrate that the proposed ASIP-based solution approaches the performance of the ASIC realization, while preserving the full flexibility of the software (RISC-based) implementation.

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Cited By

Pauls FHaas SKopsell SRoitzsch MAsmussen NFettweis G(2022)On Trustworthy Scalable Hardware/Software Platform Design2022 Smart Systems Integration (SSI)10.1109/SSI56489.2022.9901413(1-6)Online publication date: 27-Apr-2022
https://doi.org/10.1109/SSI56489.2022.9901413
Bargholz MDietrich CLohmann D(2022)PSIC: Priority-Strict Multi-Core IRQ Processing2022 IEEE 25th International Symposium On Real-Time Distributed Computing (ISORC)10.1109/ISORC52572.2022.9812796(1-9)Online publication date: 17-May-2022
https://doi.org/10.1109/ISORC52572.2022.9812796
Shantharama PThyagaturu AReisslein M(2020)Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research StudiesIEEE Access10.1109/ACCESS.2020.30082508(132021-132085)Online publication date: 2020
https://doi.org/10.1109/ACCESS.2020.3008250
Show More Cited By

Index Terms

Tomahawk: Parallelism and heterogeneity in communications signal processing MPSoCs
1. Computer systems organization
  1. Embedded and cyber-physical systems
  2. Real-time systems

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Information & Contributors

Information

Published In

cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 13, Issue 3s

Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers

March 2014

403 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/2597868

Editors:
Sandeep K. Shukla
Virginia Tech
,
Masoud Daneshtalab
University of Turku, Finland
,
Maurizio Palesi
Kore University, Italy
,
Juha Plosila
University of Turku, Finland
,
Maurizio Palesi
Kore University, Italy
,
Todor Stefanov
Leiden University, The Netherlands

Issue’s Table of Contents

Copyright © 2014 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 28 March 2014

Accepted: 01 August 2013

Revised: 01 May 2013

Received: 01 December 2012

Published in TECS Volume 13, Issue 3s

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European Union within the scope of the IMData, E2R and EMUCO projects
Bundesministerium für Bildung und Forschung

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Cited By

Pauls FHaas SKopsell SRoitzsch MAsmussen NFettweis G(2022)On Trustworthy Scalable Hardware/Software Platform Design2022 Smart Systems Integration (SSI)10.1109/SSI56489.2022.9901413(1-6)Online publication date: 27-Apr-2022
https://doi.org/10.1109/SSI56489.2022.9901413
Bargholz MDietrich CLohmann D(2022)PSIC: Priority-Strict Multi-Core IRQ Processing2022 IEEE 25th International Symposium On Real-Time Distributed Computing (ISORC)10.1109/ISORC52572.2022.9812796(1-9)Online publication date: 17-May-2022
https://doi.org/10.1109/ISORC52572.2022.9812796
Shantharama PThyagaturu AReisslein M(2020)Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research StudiesIEEE Access10.1109/ACCESS.2020.30082508(132021-132085)Online publication date: 2020
https://doi.org/10.1109/ACCESS.2020.3008250
Hille MAsmussen NBhatotia PHärtig HDan TDahlia M(2019)SemperOSProceedings of the 2019 USENIX Conference on Usenix Annual Technical Conference10.5555/3358807.3358867(709-722)Online publication date: 10-Jul-2019
https://dl.acm.org/doi/10.5555/3358807.3358867
Asmussen NRoitzsch MHärtig HDan TDahlia M(2019)M3XProceedings of the 2019 USENIX Conference on Usenix Annual Technical Conference10.5555/3358807.3358859(617-631)Online publication date: 10-Jul-2019
https://dl.acm.org/doi/10.5555/3358807.3358859
Fettweis GDorpinghaus MCastrillon JKumar ABaier CBock KEllinger FFery AFitzek FHartig HJamshidi KKissinger TLehner WMertig MNagel WNguyen GPlettemeier DSchroter MStrufe T(2019)Architecture and Advanced Electronics Pathways Toward Highly Adaptive Energy- Efficient ComputingProceedings of the IEEE10.1109/JPROC.2018.2874895107:1(204-231)Online publication date: Jan-2019
https://doi.org/10.1109/JPROC.2018.2874895
Dauphin BPacalet REnrici AApvrille L(2019)Odyn: Deadlock Prevention and Hybrid Scheduling Algorithm for Real-Time Dataflow Applications2019 22nd Euromicro Conference on Digital System Design (DSD)10.1109/DSD.2019.00023(88-95)Online publication date: Aug-2019
https://doi.org/10.1109/DSD.2019.00023
Acevedo JScheffel RWunderlich SHasler MPandi SCabrera JFitzek FFettweis GReisslein M(2018)Hardware Acceleration for RLNC: A Case Study Based on the Xtensa Processor with the Tensilica Instruction-Set ExtensionElectronics10.3390/electronics70901807:9(180)Online publication date: 8-Sep-2018
https://doi.org/10.3390/electronics7090180
Haas SSeifert TNöthen BScholze SHöppner SDixius AAdeva EAugustin TPauls FMoriam SHasler MFischer EChen YMatúš EEllguth GHartmann SSchiefer SCederström LWalter DHenker SHänzsche SUhlig JEisenreich HWeithoffer SWehn NSchüffny RMayr CFettweis G(2017)A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless ApplicationsProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062188(1-6)Online publication date: 18-Jun-2017
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Baier CKlüppelholz SWunderlich S(2017)Towards Automated Variant Selection for Heterogeneous Tiled ArchitecturesModels, Algorithms, Logics and Tools10.1007/978-3-319-63121-9_19(382-399)Online publication date: 25-Jul-2017
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