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BPM/BPM+: Software-based dynamic memory partitioning mechanisms for mitigating DRAM bank-/channel-level interferences in multicore systems

Authors:

Lei Liu,

Zehan Cui,

Yong Li,

Yungang Bao,

Mingyu Chen,

Chengyong WuAuthors Info & Claims

ACM Transactions on Architecture and Code Optimization (TACO), Volume 11, Issue 1

Article No.: 5, Pages 1 - 28

https://doi.org/10.1145/2579672

Published: 01 February 2014 Publication History

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Abstract

The main memory system is a shared resource in modern multicore machines that can result in serious interference leading to reduced throughput and unfairness. Many new memory scheduling mechanisms have been proposed to address the interference problem. However, these mechanisms usually employ relative complex scheduling logic and need modifications to Memory Controllers (MCs), which incur expensive hardware design and manufacturing overheads.

This article presents a practical software approach to effectively eliminate the interference without any hardware modifications. The key idea is to modify the OS memory management system and adopt a page-coloring-based Bank-level Partitioning Mechanism (BPM) that allocates dedicated DRAM banks to each core (or thread). By using BPM, memory requests from distinct programs are segregated across multiple memory banks to promote locality/fairness and reduce interference. We further extend BPM to BPM+ by incorporating channel-level partitioning, on which we demonstrate additional gain over BPM in many cases. To achieve benefits in the presence of diverse application memory needs and avoid performance degradation due to resource underutilization, we propose a dynamic mechanism upon BPM/BPM+ that assigns appropriate bank/channel resources based on application memory/bandwidth demands monitored through PMU (performance-monitoring unit) and a low-overhead OS page table scanning process.

We implement BPM/BPM+ in Linux 2.6.32.15 kernel and evaluate the technique on four-core and eight-core real machines by running a large amount of randomly generated multiprogrammed and multithreaded workloads. Experimental results show that BPM/BPM+ can improve the overall system throughput by 4.7%/5.9%, on average, (up to 8.6%/9.5%) and reduce the unfairness by an average of 4.2%/6.1% (up to 15.8%/13.9%).

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Index Terms

BPM/BPM+: Software-based dynamic memory partitioning mechanisms for mitigating DRAM bank-/channel-level interferences in multicore systems

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Reviews

Reviewer: Anshuman Gupta

Dynamic random access memory (DRAM) interference in shared memory systems can, as demonstrated in this paper, lead to degradation of performance. The paper proposes a software-based solution to provide isolation between applications by allocating different banks (bank-level partitioning mechanism (BPM)) and channels (BPM+) to different applications, thereby improving performance. The paper also proposes dynamically allocating the banks to applications based on their memory requirements with the objective of attaining uniform channel utilization. The paper attacks the important problem of interference on shared memory systems, and does an excellent job of quantifying the harmful effects of interference and highlighting the worsening of interference effects in the future. Moreover, the paper clearly quantifies the benefits of resource isolation and dynamic resource allocation to reaffirm these ideas, which have been proposed in the past. However, the papers software-based solution to reduce interference, determine memory requirements, and calculate dynamic allocations lacks details, is poorly evaluated, and might not be sufficiently lightweight to be useful in real systems with rapidly changing application phases or complicated memory behavior. Moreover, there is no analysis of the scalability of the proposed solution to future systems, which seem to be sharing ever-increasing resources between an increasing number of cores. Here are some key thoughts on the paper in more detail: The paper quantifies the impact of interference on fairness and throughput. The uneven and large slowdowns in applications due to bandwidth contention or row-buffer contentions can lead to degradation of overall system performance. The paper demonstrates that resource isolation can reduce interference to reduce fairness and improve throughput. This, however, comes at the cost of fragmentation: allocating banks and channels to an application that has smaller requirements can lead to underutilization. The paper demonstrates that dynamic resource allocation is required because staticfixed allocation is insufficient. The system should be able to change the resource allocation based on changing application behaviors and overall system resource availability. The papers evaluation is not very thorough. While the authors used modern benchmarks, both single threaded and multithreaded, the authors fail to show the results for all benchmark combinations under all scenarios. The results look cherry-picked. Some claims in the paper are not backed up with data. For example, dynamic allocation is evaluated in intervals of ten seconds, but why The paper shows a graph between channel utilization mismatch and performance improvement, and concludes that better balance in channel utilization leads to higher performance. This might be a correlation rather than causality, as a better channel utilization will lead to both balanced channel utilization as well as higher performance. While resource isolation is useful in reducing interference, and dynamic allocation helps to improve resource utilization, it is essential that these two mechanisms are lightweight and accurate in order to account for changing application phases. The papers software approach might be too expensive and slow to adapt to phase changes. The paper uses last level cache (LLC) miss rate to determine the applications memory behavior, which is insufficient since a low miss rate can be attributed to either large working set size or low memory-level parallelism in the application phase. The determination of application memory requirements from the LLC miss rate is not present in the paper. The authors comment that hardware solutions are complicated, but the software solution might be more expensive in terms of execution time and energy. They fail to provide any evaluation of performance and energy overheads of the mechanism. The related work section of the paper fails to look at very recent work in this area (for example, TimeCube [1]). Overall, I would recommend reading this paper to get insights into the worsening ill effects of interference in shared DRAM systems, and the qualitative and quantitative benefits of resource isolation and dynamic allocation. However, I would be cautious about the papers software-based solution to achieve these two properties. Online Computing Reviews Service

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cover image ACM Transactions on Architecture and Code Optimization

ACM Transactions on Architecture and Code Optimization Volume 11, Issue 1

February 2014

373 pages

ISSN:1544-3566

EISSN:1544-3973

DOI:10.1145/2591460

Issue’s Table of Contents

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 01 February 2014

Accepted: 01 December 2013

Revised: 01 November 2013

Received: 01 June 2013

Published in TACO Volume 11, Issue 1

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Abstract

References

Cited By

Index Terms

Recommendations

DASH: Deadline-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators

A software memory partition approach for eliminating bank-level interference in multicore systems

Reducing memory interference in multicore systems via application-aware memory channel partitioning

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