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High-Level Abstractions and Modular Debugging for FPGA Design Validation

Published: 01 February 2014 Publication History

Abstract

Design validation is the most time-consuming task in the FPGA design cycle. Although manufacturers and third-party vendors offer a range of tools that provide visibility and control of the different stages of a design, many require that the design be fully re-implemented for even simple parameter modifications or do not allow the design to be run at full speed. Designs are typically first modeled using a high-level language then later rewritten in a hardware description language, first for simulation and then later modified for synthesis. IP and third-party cores may differ during these final two stages complicating development and validation. The developed approach provides two means of directly validating synthesized hardware designs. The first allows the original high-level model written in C or C++ to be directly coupled to the synthesized hardware, abstracting away the traditional gate-level view of designs. A high-level programmatic interface allows the synthesized design to be validated directly by the software reference model. The second approach provides an alternative view to FPGAs within the scope of a traditional software debugger. This debug framework leverages partially reconfigurable regions to accelerate the modification of dynamic, software-like breakpoints for low-level analysis and provides a automatable, scriptable, command-line interface directly to a running design on an FPGA.

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Cited By

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  • (2023)Toward Software-like Debugging for FPGAs via Checkpointing and Transaction-based Co-SimulationACM Transactions on Reconfigurable Technology and Systems10.1145/355252116:2(1-24)Online publication date: 10-May-2023
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  • (2022)Stop and Look: A Novel Checkpointing and Debugging Flow for FPGAsIEEE Transactions on Computers10.1109/TC.2021.313382871:10(2513-2526)Online publication date: 1-Oct-2022
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    cover image ACM Transactions on Reconfigurable Technology and Systems
    ACM Transactions on Reconfigurable Technology and Systems  Volume 7, Issue 1
    February 2014
    117 pages
    ISSN:1936-7406
    EISSN:1936-7414
    DOI:10.1145/2589584
    • Editor:
    • Steve Wilton
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 01 February 2014
    Accepted: 01 November 2013
    Revised: 01 August 2013
    Received: 01 March 2013
    Published in TRETS Volume 7, Issue 1

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    Author Tags

    1. FPGA
    2. debug
    3. partial reconfiguration
    4. validation

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    Cited By

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    • (2023)Toward Software-like Debugging for FPGAs via Checkpointing and Transaction-based Co-SimulationACM Transactions on Reconfigurable Technology and Systems10.1145/355252116:2(1-24)Online publication date: 10-May-2023
    • (2022)mu-grindProceedings of the International Conference on Parallel Architectures and Compilation Techniques10.1145/3559009.3569671(346-358)Online publication date: 8-Oct-2022
    • (2022)Stop and Look: A Novel Checkpointing and Debugging Flow for FPGAsIEEE Transactions on Computers10.1109/TC.2021.313382871:10(2513-2526)Online publication date: 1-Oct-2022
    • (2021)StateLink: FPGA System Debugging via Flexible Simulation/Hardware Integration2021 International Conference on Field-Programmable Technology (ICFPT)10.1109/ICFPT52863.2021.9609846(1-10)Online publication date: 6-Dec-2021
    • (2020)Automated Bug Detection for High-level Synthesis of Multi-threaded Irregular ApplicationsACM Transactions on Parallel Computing10.1145/34180867:4(1-26)Online publication date: 27-Sep-2020
    • (2019)A Diagnosable Network-on-Chip for FPGA Verification of Intellectual PropertiesIEEE Design & Test10.1109/MDAT.2018.289023836:2(81-87)Online publication date: Apr-2019
    • (2018)Enabling Low Impact, Rapid Debug for Highly Utilized FPGA Designs2018 28th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2018.00022(81-813)Online publication date: Aug-2018
    • (2017)Using Efficient Path Profiling to Optimize Memory Consumption of On-Chip Debugging for High-Level SynthesisACM Transactions on Embedded Computing Systems10.1145/312656416:5s(1-19)Online publication date: 27-Sep-2017
    • (2016)Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulationProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2898002(1-6)Online publication date: 5-Jun-2016
    • (2016)A readback based general debugging framework for soft-core processors2016 IEEE 34th International Conference on Computer Design (ICCD)10.1109/ICCD.2016.7753342(568-575)Online publication date: Oct-2016
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