Simulation-based functional verification of dynamically reconfigurable systems
Article No.: 97, Pages 1 - 23
Abstract
Dynamically reconfigurable systems (DRS) implemented using field-programmable gate arrays (FPGAs) allow hardware logic to be partially reconfigured while the rest of the design continues to operate. By mapping multiple reconfigurable hardware modules to the same physical region of an FPGA, such systems are able to time-multiplex their modules at runtime and adapt themselves to changing execution requirements. This architectural flexibility introduces challenges for verifying system functionality. New simulation approaches are required to extend traditional simulation techniques to assist designers in testing and debugging the time-varying behavior of DRS. This article summarizes our previous work on ReSim, the first tool to allow cycle-accurate yet physically independent simulation of a DRS reconfiguring both its logic and state. Furthermore, ReSim-based simulation does not require changing the design for simulation purposes and thereby verifies the implementation-ready design instead of a variation of the design. We discuss the conflicting requirements of simulation accuracy and verification productivity in verifying DRS designs and describe our approach to resolve this challenge. Through a range of case studies, we demonstrate that ReSim assists designers in detecting fabric-independent bugs of DRS designs and helps to achieve verification closure of DRS design projects.
References
[1]
Florian Altenried. 2009. Time-sharing of hardware resources for image processing accelerators using dynamic partial reconfiguration. Bachelor's thesis. Technical University of Munich. (2009).
[2]
Altera. 2010. Increasing design functionality with partial and dynamic reconfiguration in 28-nm FPGAs (WP01137). Altera Inc. http://www.altera.com/literature/wp/wp-01137-stxv-dynamic-partial-reconfig.pdf.
[3]
Christian Beckhoff, Dirk Koch, and Jim Torresen. 2010. Short-circuits on FPGAs caused by partial runtime reconfiguration. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL). 596--601.
[4]
Christophe Bobda, Mateusz Majer, Ali Ahmadinia, Thomas Haller, Andre Linarth, and Jurgen Teich. 2005. The Erlangen slot machine: Increasing flexibility in FPGA-based reconfigurable platforms. In Proceedings of the International Conference on Field-Programmable Technology (FPT). 37--42.
[5]
Ediz Cetin, Oliver Diessel, Lingkan Gong, and Victor Lai. 2013. Towards bounded error recovery time in FPGA-based TMR circuits using dynamic partial reconfiguration. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL).
[6]
Christopher Claus, Johannes Zeppenfeld, Florian Muller, and Walter Stechele. 2007. Using partial-run-time reconfigurable hardware to accelerate video processing in driver assistance system. In Proceedings of the Design, Automation and Test in Europe (DATE). 1--6.
[7]
Rolf Drechsler. 2004. Advanced Formal Verification. Kluwer Academic Publishers.
[8]
Stephanie Drzevitzky, Uwe Kastens, and Marco Platzner. 2009. Proof-carrying hardware: Towards runtime verification of reconfigurable modules. In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig). 189--194.
[9]
Lingkan Gong. 2013. ReSim case studies. http://code.google.com/p/resim-simulating-partial-reconfiguration/.
[10]
Lingkan Gong and Oliver Diessel. 2011a. Modeling dynamically reconfigurable systems for simulation-based functional verification. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). 9--16.
[11]
Lingkan Gong and Oliver Diessel. 2011b. ReSim: A reusable library for RTL simulation of dynamic partial reconfiguration. In Proceedings of the International Conference on Field-Programmable Technology (FPT). 1--8.
[12]
Lingkan Gong and Oliver Diessel. 2012. Functionally verifying state saving and restoration in dynamically reconfigurable systems. In Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA). 241--244.
[13]
Lingkan Gong, Oliver Diessel, Johny Paul, and Walter Stechele. 2013. RTL simulation of high performance dynamic reconfiguration: A video processing case study. In Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS).
[14]
Simen Gimle Hansen, Dirk Koch, and Jim Torresen. 2013. Simulation framework for cycle-accurate RTL modeling of partial run-time reconfiguration in VHDL. In Proceedings of the International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC). 1--8.
[15]
Yoshihiro Ichinomiya, Shiro Tanoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, and Toshinori Sueyoshi. 2010. Improving the robustness of a softcore processor against SEUs by using TMR and partial reconfiguration. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). 47--54.
[16]
Abelardo Jara-Berrocal and Ann Gordon-Ross. 2010. VAPRES: A virtual architecture for partially reconfigurable embedded systems. In Proceedings of the Design, Automation and Test in Europe (DATE). 837.
[17]
Wayne Luk, Nabeel Shirazi, and Peter Y. K. Cheung. 1997. Compilation tools for run-time reconfigurable designs. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). 56--65.
[18]
Katarina Paulsson, Michael Hubner, Markus Jung, and Jurgen Becker. 2006. Methods for run-time failure recognition and recovery in dynamic and partial reconfigurable systems based on Xilinx Virtex-II Pro FPGAs. In Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures. 1--6.
[19]
Andreas Raabe, Philipp A. Hartmann, and Joachim K. Anlauf. 2008. ReChannel: Describing and simulating reconfigurable hardware in SystemC. ACM Trans. Des. Autom. Electron. Syst. 13, 1, 15.
[20]
Ian Robertson and James Irvine. 2004. A design flow for partially reconfigurable hardware. ACM Trans. Embed. Comput. Syst. 3, 2, 257--283.
[21]
Andreas Schallenberg, Wolfgang Nebel, Andreas Herrholz, and Philipp A. Hartmann. 2009. OSSS+R: A framework for application level modelling and synthesis of reconfigurable systems. In Proceedings of the Design, Automation and Test in Europe (DATE) 970--975.
[22]
Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, and Wayne Luk. 2007. Run-time integration of reconfigurable video processing systems. IEEE Trans. VLSI Syst. 15, 9, 1003--1016.
[23]
Andre Seffrin, Alexander Biedermann, and Sorin A. Huss. 2010. Tiny-n: A novel formal method for specification, analysis, and verification of dynamic partial reconfiguration processes. In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (CSREA). 1--6.
[24]
Satnam Singh and Carl J. Lillieroth. 1999. Formal verification of reconfigurable cores. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). 25--32.
[25]
Simon Tam and Martin Kellermann. 2010. Fast Configuration of PCI Express Technology through Partial Reconfiguration (XAPP883). Xilinx Inc.
[26]
Tim Todman, Peter Boehm, and Wayne Luk. 2012. Verification of streaming hardware and software codesigns. In Proceedings of the International Conference on Field-Programmable Technology (FPT). 147--150.
[27]
Michael J. Wirthlin and Brad L. Hutchings. 1998. Improving functional density using run-time circuit reconfiguration. IEEE Trans. VLSI Syst. 6, 2, 247--256.
[28]
Xilinx. 2009a. PlanAhead software tutorial: Partial reconfiguration of a processor peripheral (UG744). Xilinx Inc.
[29]
Xilinx. 2009b. Virtex-4 FPGA Configuration User Guide (UG071). Xilinx Inc.
[30]
Xilinx. 2010a. ChipScope Pro 12.1 software and cores (UG029). Xilinx Inc.
[31]
Xilinx. 2010b. EDK concepts, tools and techniques (UG683). Xilinx Inc.
[32]
Xilinx. 2010c. Partial Reconfiguration User Guide (UG702). Xilinx Inc.
[33]
Xilinx. 2010d. Virtex-5 FPGA Configuration User Guide (UG191). Xilinx Inc.
[34]
Xilinx. 2010e. Virtex-6 FPGA Configuration User Guide (UG360). Xilinx Inc.
[35]
Xilinx. 2011. Partial reconfiguartion - Can I insert chipscope cores within reconfigurable modules? Xilinx Inc. http://www.xilinx.com/support/answers/42899.
[36]
Xilinx. 2013. 7 Series FPGAs Configuration User Guide (UG470). Xilinx Inc.
Index Terms
- Simulation-based functional verification of dynamically reconfigurable systems
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November 2014
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Publication History
Published: 10 March 2014
Accepted: 01 October 2013
Received: 01 May 2013
Published in TECS Volume 13, Issue 4
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