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HEAT: hierarchical energy analysis tool

Authors:

Janardhan H. Satyanarayana,

Keshab K. ParhiAuthors Info & Claims

DAC '96: Proceedings of the 33rd annual Design Automation Conference

Pages 9 - 14

https://doi.org/10.1145/240518.240520

Published: 01 June 1996 Publication History

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Cited By

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Hashemi Namin SWu HAhmadi M(2017)Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring TechniqueIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.258598025:2(441-449)Online publication date: 1-Feb-2017
https://dl.acm.org/doi/10.1109/TVLSI.2016.2585980
Ramprasad SShanbha NHajj I(2006)Analytical estimation of signal transition activity from word-level statisticsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.64403316:7(718-733)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.644033
Zyuban V(2003)Optimization of scannable latches for low energyIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2003.81432211:5(778-788)Online publication date: 1-Oct-2003
https://dl.acm.org/doi/10.1109/TVLSI.2003.814322
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Index Terms

HEAT: hierarchical energy analysis tool
1. Applied computing
  1. Physical sciences and engineering
2. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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Published In

DAC '96: Proceedings of the 33rd annual Design Automation Conference

June 1996

839 pages

ISBN:0897917790

DOI:10.1145/240518

Chairmen:
Thomas P. Pennino
Bell Labs, Holmdel, NJ
,
Ellen J. Yoffa
IBM Corp., Yorktown Heights, NY

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 1996

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Conference

DAC96

Sponsor:

EDAC
SIGDA
IEEE-CAS

DAC96: The 33rd Design Automation Conference

June 3 - 7, 1996

Nevada, Las Vegas, USA

Acceptance Rates

DAC '96 Paper Acceptance Rate 142 of 377 submissions, 38%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

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Cited By

View all

Hashemi Namin SWu HAhmadi M(2017)Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring TechniqueIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.258598025:2(441-449)Online publication date: 1-Feb-2017
https://dl.acm.org/doi/10.1109/TVLSI.2016.2585980
Ramprasad SShanbha NHajj I(2006)Analytical estimation of signal transition activity from word-level statisticsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.64403316:7(718-733)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.644033
Zyuban V(2003)Optimization of scannable latches for low energyIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2003.81432211:5(778-788)Online publication date: 1-Oct-2003
https://dl.acm.org/doi/10.1109/TVLSI.2003.814322
Kim KKim THwang TKang SLiu C(2002)Logic transformation for low-power synthesisACM Transactions on Design Automation of Electronic Systems10.1145/544536.5445397:2(265-283)Online publication date: 1-Apr-2002
https://dl.acm.org/doi/10.1145/544536.544539
Zyuban VMeltzer DMacii EDe VIrwin M(2001)Clocking strategies and scannable latches for low power appliacationsProceedings of the 2001 international symposium on Low power electronics and design10.1145/383082.383181(346-351)Online publication date: 6-Aug-2001
https://dl.acm.org/doi/10.1145/383082.383181
Parhi K(2001)Approaches to low-power implementations of DSP systemsIEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications10.1109/81.95601648:10(1214-1224)Online publication date: Jan-2001
https://doi.org/10.1109/81.956016
Shalash AParhi K(2000)Power Efficient Folding of Pipelined LMS Adaptive Filters with Applications to Wireline Digital CommunicationsJournal of VLSI Signal Processing Systems10.5555/352191.281297725:3(199-213)Online publication date: 1-Jul-2000
https://dl.acm.org/doi/10.5555/352191.2812977
Sundararajan VParhi KYoshida K(2000)Synthesis of low power folded programmable coefficient FIR digital filters (short paper)Proceedings of the 2000 Asia and South Pacific Design Automation Conference10.1145/368434.368595(153-156)Online publication date: 28-Jan-2000
https://dl.acm.org/doi/10.1145/368434.368595
Sundararajan VParhi K(2000)Synthesis of low power folded programmable coefficient FIR digital filtersProceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106)10.1109/ASPDAC.2000.835087(153-156)Online publication date: 2000
https://doi.org/10.1109/ASPDAC.2000.835087
Song LParhi KKuroda INishitani T(2000)Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/92.8314368:2(160-172)Online publication date: 1-Apr-2000
https://dl.acm.org/doi/10.1109/92.831436
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