research-article

Robust architectural support for transactional memory in the power architecture

Authors:

Harold W. Cain,

Maged M. Michael,

Derek Williams,

Hung LeAuthors Info & Claims

ISCA '13: Proceedings of the 40th Annual International Symposium on Computer Architecture

Pages 225 - 236

https://doi.org/10.1145/2485922.2485942

Published: 23 June 2013 Publication History

Abstract

On the twentieth anniversary of the original publication [10], following ten years of intense activity in the research literature, hardware support for transactional memory (TM) has finally become a commercial reality, with HTM-enabled chips currently or soon-to-be available from many hardware vendors. In this paper we describe architectural support for TM added to a future version of the Power ISA™. Two imperatives drove the development: the desire to complement our weakly-consistent memory model with a more friendly interface to simplify the development and porting of multithreaded applications, and the need for robustness beyond that of some early implementations. In the process of commercializing the feature, we had to resolve some previously unexplored interactions between TM and existing features of the ISA, for example translation shootdown, interrupt handling, atomic read-modify-write primitives, and our weakly consistent memory model. We describe these interactions, the overall architecture, and discuss the motivation and rationale for our choices of architectural semantics, beyond what is typically found in reference manuals.

References

[1]

ARM Arch. Reference Manual. ARM Ltd., 2005.

[2]

L. Baugh and C. Zilles. An analysis of I/O and syscalls in critical sections and their implications for transactional memory. In Proc. of the 2008 Intl. Symp. on Performance Analysis of Systems and Software.

Digital Library

[3]

C. Blundell, E. C. Lewis, and M. M. K. Martin. Unrestricted transactional memory: Supporting I/O and system calls within transactions. Technical Report CIS-06-09, Department of Computer and Information Science, University of Pennsylvania, Apr 2006.

[4]

H.-J. Boehm and S. V. Adve. Foundations of the C++ concurrency memory model. In Proc. of the 2008 Conf. on Programming language design and implementation, 2008.

Digital Library

[5]

J. Chung, C. C. Minh, A. McDonald, T. Skare, H. Chafi, B. D. Carlstrom, C. Kozyrakis, and K. Olukotun. Tradeoffs in transactional memory virtualization. In Proc. of the 12th Intl. Conf. on Architectural Support for Programming Languages and Operating Systems, 2006.

Digital Library

[6]

W. W. Collier. Reasoning about parallel architectures. Prentice-Hall, Inc., 1992.

Digital Library

[7]

D. Dice, Y. Lev, M. Moir, and D. Nussbaum. Early experience with a commercial hardware transactional memory implementation. In Proc. of the 14th Intl. Conference on Architectural Support for Programming Languages and Operating Systems, 2009.

Digital Library

[8]

L. Hammond, V. Wong, M. Chen, B. D. Carlstrom, J. D. Davis, B. Hertzberg, M. K. Prabhu, H. Wijaya, C. Kozyrakis, and K. Olukotun. Transactional memory coherence and consistency. In Proc. of the 31st Intl. Symp. on Computer Architecture. Jun 2004.

Digital Library

[9]

T. Harris. Exceptions and side-effects in atomic blocks. Sci. Comput. Program., 58(3), Dec. 2005.

Digital Library

[10]

M. Herlihy and J. E. B. Moss. Transactional memory: architectural support for lock-free data structures. In Proc. of the 20th Intl. Symp. on Computer Architecture, 1993.

Digital Library

[11]

O. S. Hofmann, D. E. Porter, C. J. Rossbach, H. E. Ramadan, and E. Witchel. Solving difficult HTM problems without difficult hardware. In TRANSACT '07: 2nd Workshop on Transactional Computing, August 2007.

[12]

IBM Corporation. Power Instruction Set Architecture v.2.06B, July 2010.

[13]

Intel Corporation. Intel IA-64 Architecture Software Developers Manua l, Volume 2: IA-64 System Architecture, Revision 1.1, July 2000.

[14]

Intel Corporation. Intel 64 and IA-32 Architectures Software Developer's Manual, August 2012.

[15]

Intel Corporation. Intel Architecture Instruction Set Extensions Programming Reference: Chapter 8: Intel Transactional Synchronization Extensions, Feb. 2012.

[16]

C. Jacobi, T. Slegel, and D. Greiner. Transactional memory architecture and implementation for IBM System z. In Proc. of the 45th Intl. Symposium on Microarchitecture, December 2012.

Digital Library

[17]

M. M. K. Martin, C. Blundell, and E. Lewis. Subtleties of transactional memory atomicity semantics. Computer Architecture Letters, 5(2), 2006.

Digital Library

[18]

A. McDonald, J. Chung, B. D. Carlstrom, C. C. Minh, H. Chafi, C. Kozyrakis, and K. Olukotun. Architectural semantics for practical transactional memory. In Proc. of the 33rd Intl. Symposium on Computer Architecture, 2006.

Digital Library

[19]

M. Moir, K. Moore, and D. Nussbaum. The adaptive transactional memory test platform: A tool for experimenting with transactional code for Rock. In TRANSACT '08: 3rd Workshop on Transactional Computing, February 2008.

Digital Library

[20]

M. J. Moravan, J. Bobba, K. E. Moore, L. Yen, M. D. Hill, B. Liblit, M. M. Swift, and D. A. Wood. Supporting nested transactional memory in LogTM. In Proc. of the 12th Intl. Conf. on Architectural support for programming languages and operating systems, 2006.

Digital Library

[21]

T. Nakaike and M. M. Michael. Lock elision for read-only critical sections in java. In Proc. of the 2010 Conf. on Programming Language Design and Implementation.

Digital Library

[22]

N. Neelakantam, R. Rajwar, S. Srinivas, U. Srinivasan, and C. Zilles. Hardware atomicity for reliable software speculation. In Proc. of the 34th Intl. Symposium on Computer Architecture, 2007.

Digital Library

[23]

S. J. Patel and S. S. Lumetta. rePLay: A hardware framework for dynamic optimization. IEEE Transactions on Computer Systems, 50(6), June 2001.

Digital Library

[24]

R. Rajwar and J. R. Goodman. Speculative lock elision: enabling highly concurrent multi-threaded execution. In Proc. of the 34th Intl. Symposium on Microarchitecture, 2001.

Digital Library

[25]

R. Rajwar, M. Herlihy, and K. Lai. Virtualizing transactional memory. In Proc. of the 32nd Intl. Symp. on Computer Architecture, 2005.

Digital Library

[26]

S. Sarkar, K. Memarian, S. Owens, M. Batty, P. Sewell, L. Maranget, J. Alglave, and D. Williams. Synchronising C/C++ and POWER. In Proc. of the 33rd Conf. on Programming Language Design and Implementation, 2012.

Digital Library

[27]

S. Sarkar, P. Sewell, J. Alglave, L. Maranget, and D. Williams. Understanding POWER multiprocessors. In Proc. of the 32nd Conf. on Programming Language Design and Implementation, 2011.

Digital Library

[28]

L. Su and M. H. Lipasti. Speculative optimization using hardware-monitored guarded regions for java virtual machines. In Proc. of the 3rd Intl. Conf. on Virtual execution environments, 2007.

Digital Library

[29]

D. L. Weaver and T. Germond, editors. SPARC Architecture Manual V9). PTR Prentice Hall, 1994.

[30]

C. Zilles and L. Baugh. Extending hardware transactional memory to support nonbusy waiting and nontransactional actions. In Proc. of the First Workshop on Languages, Compilers, and Hardware Support for Transactional Computing. June 2006.

Cited By

Wan LChao FLi QHan J(2024)LockillerTM: Enhancing Performance Lower Bounds in Best-Effort Hardware Transactional Memory2024 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS57955.2024.00081(865-875)Online publication date: 27-May-2024
https://doi.org/10.1109/IPDPS57955.2024.00081
Jain AKadiyala DDaglis A(2023)Safety Hints for HTM Capacity Abort Mitigation2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071113(206-219)Online publication date: Feb-2023
https://doi.org/10.1109/HPCA56546.2023.10071113
Busch CChlebus BHerlihy MPopovic MPoudel PSharma G(2023)Flexible scheduling of transactional memory on treesTheoretical Computer Science10.1016/j.tcs.2023.114184(114184)Online publication date: Sep-2023
https://doi.org/10.1016/j.tcs.2023.114184
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Published In

cover image ACM Other conferences

ISCA '13: Proceedings of the 40th Annual International Symposium on Computer Architecture

June 2013

686 pages

ISBN:9781450320795

DOI:10.1145/2485922

General Chair:
Avi Mendelson
Technion

ACM SIGARCH Computer Architecture News Volume 41, Issue 3
ICSA '13
June 2013
666 pages
ISSN:0163-5964
DOI:10.1145/2508148
Issue’s Table of Contents

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 23 June 2013

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June 23 - 27, 2013

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ISCA '13 Paper Acceptance Rate 56 of 288 submissions, 19%;

Overall Acceptance Rate 543 of 3,203 submissions, 17%

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Cited By

Wan LChao FLi QHan J(2024)LockillerTM: Enhancing Performance Lower Bounds in Best-Effort Hardware Transactional Memory2024 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS57955.2024.00081(865-875)Online publication date: 27-May-2024
https://doi.org/10.1109/IPDPS57955.2024.00081
Jain AKadiyala DDaglis A(2023)Safety Hints for HTM Capacity Abort Mitigation2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071113(206-219)Online publication date: Feb-2023
https://doi.org/10.1109/HPCA56546.2023.10071113
Busch CChlebus BHerlihy MPopovic MPoudel PSharma G(2023)Flexible scheduling of transactional memory on treesTheoretical Computer Science10.1016/j.tcs.2023.114184(114184)Online publication date: Sep-2023
https://doi.org/10.1016/j.tcs.2023.114184
Kim SHan MBaek W(2022)DPrime+DAbort: A High-Precision and Timer-Free Directory-Based Side-Channel Attack in Non-Inclusive Cache Hierarchies using Intel TSX2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA53966.2022.00014(67-81)Online publication date: Apr-2022
https://doi.org/10.1109/HPCA53966.2022.00014
Poudel PSharma G(2021)Adaptive Versioning in Transactional Memory SystemsAlgorithms10.3390/a1406017114:6(171)Online publication date: 31-May-2021
https://doi.org/10.3390/a14060171
Ostrovsky OMorrison AGupta RShen X(2020)Scaling concurrent queues by using HTM to profit from failed atomic operationsProceedings of the 25th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming10.1145/3332466.3374511(89-101)Online publication date: 19-Feb-2020
https://dl.acm.org/doi/10.1145/3332466.3374511
Busch CHerlihy MPopovic MSharma G(2020)Dynamic Scheduling in Distributed Transactional Memory2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS47924.2020.00094(874-883)Online publication date: May-2020
https://doi.org/10.1109/IPDPS47924.2020.00094
Dongol BJagadeesan RRiely JHollingsworth JKeidar I(2019)Modular transactionsProceedings of the 24th Symposium on Principles and Practice of Parallel Programming10.1145/3293883.3295708(82-93)Online publication date: 16-Feb-2019
https://dl.acm.org/doi/10.1145/3293883.3295708
Shull TChoi JGarzaran MTorrellas J(2019)NoMap: Speeding-Up JavaScript Using Hardware Transactional Memory2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2019.00054(412-425)Online publication date: Feb-2019
https://doi.org/10.1109/HPCA.2019.00054
Quislant RGutierrez EZapata EPlata O(2019)Improving hardware transactional memory parallelization of computational geometry algorithms using privatizing transactionsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2019.04.018Online publication date: May-2019
https://doi.org/10.1016/j.jpdc.2019.04.018
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