research-article

Designing best effort networks-on-chip to meet hard latency constraints

Authors:

Ciprian Seiculescu,

Srinivasan Murali,

Hamid Sarbazi-Azad,

Giovanni De MicheliAuthors Info & Claims

ACM Transactions on Embedded Computing Systems (TECS), Volume 12, Issue 4

Article No.: 108, Pages 1 - 23

https://doi.org/10.1145/2485984.2485996

Published: 03 July 2013 Publication History

Abstract

Many classes of applications require Quality of Service (QoS) guarantees from the system interconnect. In Networks-on-Chip (NoC) QoS guarantees usually translate into bandwidth and latency constraints for the traffic flows and require hardware support in the NoC fabric and its interfaces. In this article we present a novel NoC synthesis framework to automatically build networks that meet hard latency constraints of end-to-end traffic streams without requiring specialized hardware for the network components. The hard latency constraints are met by carefully designing the NoC topology and selecting the appropriate routes for flow using lean best-effort network components. We perform experiments on several System on Chip (SoC) benchmarks. We compared against a topology synthesis method with no support for real-time constraints and we show that the proposed method can produce topologies that can meet significantly tighter worst case latency constraints (on average 44%). We also show that the tightest worst case latency can be provided with little overhead on power consumption (on average 8.5%).

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Cited By

Rahmati DSarbazi-Azad H(2018)Classified Round Robin: A Simple Prioritized Arbitration to Equip Best Effort NoCs With Effective Hard QoSIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.269326337:1(257-269)Online publication date: Jan-2018
https://doi.org/10.1109/TCAD.2017.2693263
Fraccaroli EStefanni FRizzi RQuaglia DFummi F(2018)Network Synthesis for Distributed Embedded SystemsIEEE Transactions on Computers10.1109/TC.2018.281279767:9(1315-1330)Online publication date: 1-Sep-2018
https://doi.org/10.1109/TC.2018.2812797
Phanibhushana BKundu S(2014)Network-on-Chip Design for Heterogeneous Multiprocessor System-on-ChipProceedings of the 2014 IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2014.96(486-491)Online publication date: 9-Jul-2014
https://dl.acm.org/doi/10.1109/ISVLSI.2014.96

Index Terms

Designing best effort networks-on-chip to meet hard latency constraints
1. Networks
  1. Network types
    1. Packet-switching networks

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Published In

cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 12, Issue 4

Special Section on Wireless Health Systems, On-Chip and Off-Chip Network Architectures

June 2013

288 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/2485984

Issue’s Table of Contents

Copyright © 2013 ACM.

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 03 July 2013

Accepted: 01 September 2011

Revised: 01 July 2011

Received: 01 March 2011

Published in TECS Volume 12, Issue 4

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Cited By

Rahmati DSarbazi-Azad H(2018)Classified Round Robin: A Simple Prioritized Arbitration to Equip Best Effort NoCs With Effective Hard QoSIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.269326337:1(257-269)Online publication date: Jan-2018
https://doi.org/10.1109/TCAD.2017.2693263
Fraccaroli EStefanni FRizzi RQuaglia DFummi F(2018)Network Synthesis for Distributed Embedded SystemsIEEE Transactions on Computers10.1109/TC.2018.281279767:9(1315-1330)Online publication date: 1-Sep-2018
https://doi.org/10.1109/TC.2018.2812797
Phanibhushana BKundu S(2014)Network-on-Chip Design for Heterogeneous Multiprocessor System-on-ChipProceedings of the 2014 IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2014.96(486-491)Online publication date: 9-Jul-2014
https://dl.acm.org/doi/10.1109/ISVLSI.2014.96

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