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A novel and improved design of a ternary CNTFET-based cell

Published: 02 May 2013 Publication History

Abstract

A novel ternary CNTFET-based SRAM cell is proposed in this paper; the operation of this CNTFET SRAM is nearly independent of the ternary values, therefore it is said to be balanced. Different from previous ternary cells, the proposed cell does not require a read buffer for changing the voltage level of the read bit line, because it uses additional CNTFETs to sink the bit lines to ground. By using four additional CNTFETs for ternary operation, a conventional (two-valued) sense amplifier is then used for output response. The contribution of this paper is not restricted to the design of the SRAM cell, but also the systematic modifications of the CNTFETs to substantially improve specific performance metrics. CNTFET features (such as sizing) and performance metrics (such as SNM, power delay product (PDP) and write/read times) are considered and assessed in detail. Extensive simulation results are provided to show that the proposed ternary SRAM cell has better performance compared to a previous CNTFET-based ternary cell as well as binary-based cells (implemented by either MOSFET or CNTFET).

References

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P. C. Balla, A. Antoniou, "Low power dissipation MOS ternary logic family," IEEE Journal of Solid-State Circuits, vol. 19, no. 5, pp. 739--749, 1984.
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Cited By

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  • (2022)CNTFET-Based Ternary Multiply-and-Accumulate UnitElectronics10.3390/electronics1109145511:9(1455)Online publication date: 30-Apr-2022
  • (2021)Low-Power and High-Performance Ternary SRAM Designs With Application to CNTFET TechnologyIEEE Transactions on Nanotechnology10.1109/TNANO.2021.309612320(562-566)Online publication date: 2021
  • (2020)A Half Adder Design Based on Ternary Multiplexers in Carbon Nano-Tube Field Effect Transistor (CNFET) TechnologyECS Journal of Solid State Science and Technology10.1149/2162-8777/abb5889:8(081001)Online publication date: 11-Sep-2020
  • Show More Cited By

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        cover image ACM Conferences
        GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
        May 2013
        368 pages
        ISBN:9781450320320
        DOI:10.1145/2483028
        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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        Published: 02 May 2013

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        Author Tags

        1. cntfet
        2. process variation
        3. ternary sram design

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        GLSVLSI '13 Paper Acceptance Rate 76 of 238 submissions, 32%;
        Overall Acceptance Rate 312 of 1,156 submissions, 27%

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        Cited By

        View all
        • (2022)CNTFET-Based Ternary Multiply-and-Accumulate UnitElectronics10.3390/electronics1109145511:9(1455)Online publication date: 30-Apr-2022
        • (2021)Low-Power and High-Performance Ternary SRAM Designs With Application to CNTFET TechnologyIEEE Transactions on Nanotechnology10.1109/TNANO.2021.309612320(562-566)Online publication date: 2021
        • (2020)A Half Adder Design Based on Ternary Multiplexers in Carbon Nano-Tube Field Effect Transistor (CNFET) TechnologyECS Journal of Solid State Science and Technology10.1149/2162-8777/abb5889:8(081001)Online publication date: 11-Sep-2020
        • (2020)Implementation of Triple-Value Memory Cell Based Carbon Nanotube Field-Effect TransistorAEU - International Journal of Electronics and Communications10.1016/j.aeue.2020.153392(153392)Online publication date: Jul-2020
        • (2018)A novel design of low power and high read stability Ternary SRAM (T-SRAM), memory based on the modified Gate Diffusion Input (m-GDI) method in nanotechnologyMicroelectronics Journal10.1016/j.mejo.2016.10.00958:C(44-59)Online publication date: 26-Dec-2018
        • (2018)Novel and general carbon nanotube FET-based circuit designs to implement all of the 39 ternary functions without mathematical operationsMicroelectronics Journal10.1016/j.mejo.2013.06.00244:9(794-801)Online publication date: 27-Dec-2018
        • (2016)Design and process variation analysis of CNTFET-based ternary memory cellsIntegration, the VLSI Journal10.1016/j.vlsi.2016.02.00354:C(97-108)Online publication date: 1-Jun-2016
        • (2013)A Novel CNTFET-based Ternary Full AdderCircuits, Systems, and Signal Processing10.1007/s00034-013-9672-633:3(665-679)Online publication date: 12-Oct-2013

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